Panasonic F77G User Manual page 116

Chapter 3 Interrupts
Timer 0 Interrupt Control Register (TM0ICR)
The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
7 6
TM0 TM0
TM0ICR
LV1 LV0
Figure 3-2-8
III - 22
Control Registers
5 4 3 2
- - - -
Timer 0 Interrupt Control Register (TM0ICR : x'03FE9', R/W)
1 0
(At reset : 0 0 - - - - 0 0)
TM0IE TM0IR
TM0IR
0
1
TM0IE
0
1
TM0
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
TM0
Interrupt level flag
LV0