Panasonic F77G User Manual page 128

Chapter 3 Interrupts
Serial Interface 3 Interrupt Control Register (SC3ICR)
The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3
interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when
the maskable interrupt enable flag (MIE) of PSW is "0".
7
SC3 SC3
SC3ICR
LV1 LV0
Figure 3-2-23
III - 34
Control Registers
6 5 4 3
- - -
Serial Interface 3 Interrupt Control Register (SC3ICR : x'03FF9', R/W)
2 1 0
- SC3IE SC3IR
SC3
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
(At reset : 0 0 - - - - 0 0)
Interrupt request flag
SC3IR
0 No interrupt request
1 Interrupt request generated
Interrupt enable flag
SC3IE
0 Disable interrupt
1 Enable interrupt
SC3
Interrupt level flag
LV0