Block Diagram - Panasonic F77G User Manual

2-1-1

Block Diagram

Address registers
Stack pointer
SP
ABUS
BBUS
Program
counter
Incrementer
Program address
ROM bus
Internal ROM
Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals
Clock generator
to CPU blocks.
Generates addresses for the instructions to be inserted into the instruction queue. Normally
Program counter incremented by sequencer indication, but may be set to branch destination address or ALU operation
result when branch instructions or interrupts occur.
Instruction queue Stores up to 2 bytes of pre-fetched instructions.
Decodes the instruction queue, sequentially generates the control signals needed for instruction
Instruction decoder
execution, and executes the instruction by controlling the blocks within the chip.
Instruction execution Controls CPU block operations in response to the result decoded by the instruction decoder and
controller interrupt requests.
Executes arithmetic operations, logic operations, shift operations, and calculates operand addresses
ALU
for register relative indirect addressing mode.
Internal ROM, RAM Assigned to the execution program, data and stack region.
Stores the addresses specifying memory for data transfer. Stores the base address for register relative
Address register
indirect addressing mode.
Data register Holds data for operations. Two 8-bit registers can be connected to form a 16-bit register.
Interrupt controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing.
Controls connection of CPU internal bus and CPU external bus. Includes bus usage arbitration
Bus controller
function.
Internal peripheral Includes peripheral functions (timer, serial interface, A/D converter, D/A converter, etc.) Peripheral
functions functions vary with model.
Data registers
D0
D1
A0 D2
A1 D3
ALU
Bus controller
RAM bus
Internal RAM
Figure 2-1-1 Block Diagram and Function
Processor status word
T1
T2
PSW
Instruction execution
Instruction
queue
Operand address
Chapter 2 CPU Basics
Clock
Source oscillation
generator
controller
Instruction decoder
Interrupt
controller
Interrupt bus
Peripheral expansion bus
Internal peripheral
functions
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