Panasonic F77G User Manual page 115

External Interrupt 4 Control Register (IRQ4ICR)
The external interrupt 4 control register (IRQ4ICR) controls interrupt level of external interrupt 4, active
edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
7 6
IRQ4 IRQ4
IRQ4ICR
LV1 LV0
Figure 3-2-6
5 4 3 2
- - -
REDG4
External Interrupt 4 Control Register (IRQ4ICR : x'03FE6', R/W)
1 0
(At reset : 0 0 0 - - - 0 0)
IRQ4IE IRQ4IR
IRQ4IR
0
1
IRQ4IE
0
1
REDG4
0
1
IRQ4
LV1
The CPU has interrupt levels from 0 to 3. These
flags set the interrupt level for interrupt requests.
Chapter 3 Interrupts
External interrupt request flag
No interrupt request
Interrupt request generated
External interrupt enable flag
Disable interrupt
Enable interrupt
External interrupt active edge flag
Falling edge
Rising edge
IRQ4
Interrupt level flag for external interrupt
LV0
Control Registers
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