Panasonic F77G User Manual page 30

Chapter 1 Overview
Name No.
P20 27
P21 28
P22 29
P23 30
P24 31
P27 14
P50 32
P51 33
P52 34
P53 35
P54 36
P60 37
P61 38
P62 39
P63 40
P64 41
P65 42
P66 43
P67 44
P70 45
P71 46
P72 47
P73 48
P74 49
P75 50
P76 51
P77 52
P80 60
P81 59
P82 58
P83 57
P84 56
P85 55
P86 54
P87 53
PA0 62
PA1 63
PA2 64
PA3 1
PA4 2
PA5 3
PA6 4
I - 12
Pin Description
Table 1-3-4
I/O Function Other Function
I/O I/O port 2 IRQ0
IRQ1, ACZ
IRQ2
IRQ3
IRQ4
Input I/O port 2 NRST
I/O I/O port 5 SBI3
SBO3,
SBT3
SDA4A
SCL4A
I/O I/O port 6 SDO0, KEY0
SDO1, KEY1
SDO2, KEY2
SDO3, KEY3
SDO4, KEY4
SDO5, KEY5
SDO6, KEY6
SDO7, KEY7
I/O I/O port 7 SBO0B, TXD0B
SBI0B, RXD0B
SBT0B
SBO1B, TXD1B
SBI1B, RXD1B
SBT1B
TCI01
TCI05
I/O I/O port 8 LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
I/O I/O port A AN0, DA0
AN1, DA1
AN2
AN3
AN4
AN5
AN6
Pin Function Summary (2/6)
5-Bit CMOS tri-state I/O port.
A pull-up resistor for each bit can be selected
individually by the P2PLU register.
At reset, pull-up resistors are disabled
(high impedance output).
P27 has an n-channel open-drain configuration.
When "0" is written and the reset is initiated by
software, a low level will be output.
5-Bit CMOS tri-state I/O port.
Each bit can be set individually as either an input
or output by the P5DIR register. A pull-up resistor
for each bit can be selected individually by the
P5PLU register. At reset, the P50t o P54 input
mode is selected and pull- up resistors are
disabled. (high impedance output)
8-Bit CMOS tri-state I/O port.
Each bit can be set individually as either an input
or output by the P6DIR register. A pull-up resistor
for each bit can be selected individually by the
P6PLU register.
At reset, the P60 to P67 input mode is selected
and pull- up resistors are disabled.
(high impedance output)
8-Bit CMOS tri-state I/O port.
Each bit can be set individually as either an input
or output by the P7DIR register. A pull-up/pull-
down resistor for each bit can be selected
individually by the P7PLU register. However,
pull-up and pull-down resistors cannot be mixed.
At reset, the P70to P77 input mode is selected
and pull- up resistors are disabled. (high
impedance output)
8-Bit CMOS tri-state I/O port. Each bit can be set
individually as either an input or output by the
P8DIR register. A pull-up resistor for each bit can
be selected individually by the P8PLU register.
When configured as outputs, these pins can
drive LEDs directly. At reset, the P80to P87 input
mode is selected and pull- up resistors are
disabled. (high impedance output)
6-Bit I/O port. A pull-up or pull-down resistor for
each bit can be selected individually by the
PAPLUD resister. However, pull-up and pull-
down resistors cannot be mixed. At reset, the
PA0 to PA6 input mode is selected and pull- up
resistors are disabled. (high impedance output)
Description