Chapter 2 CPU Basics
2-1-7
Processor Status Word
Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask
level, and maskable interrupt enable. PSW is automatically pushed onto the stack when an interrupt
occurs and is automatically popped when return from the interrupt service routine.
7
PSW
Reserved
II - 8
Overview
6
5
4
MIE
IM1
IM0
Figure 2-1-3
3
2
1
VF
NF
CF
Processor Status Word(PSW)
0
ZF
( At reset : 0 0 0 0 0 0 0 0 )
Zero flag
ZF
0
Operation result is not "0".
Operation result is "0".
1
CF
Carry flag
A carry or a borrow from MSB
0
did not occur.
A carry or a borrow from MSB
1
occured.
NF
Negative flag
MSB of operation results is "0".
0
MSB of operation results is "1".
1
VF
Overflow flag
0
Overflow did not occur.
1
Overflow occured.
Interrupt mask level
IM1 to 0
Controls maskable interrupt acceptance.
MIE
Maskable interrupt enable
All maskable interrupts are
0
disabled.
(xxxLVn,xxxIE) for each interrupt
1
are enabled.
Set always "0".
Reserved