Panasonic F77G User Manual page 111

External Interrupt 0 Control Register (IRQ0ICR)
The external interrupt 0 control register (IRQ0ICR) controls interrupt level of the external interrupt 0,
active edge, interrupt enable and interrupt request. Interrupt control register should be operated when
the maskable interrupt enable flag (MIE) of PSW is "0".
7 6
IRQ0 IRQ0
IRQ0ICR
LV1 LV0
Figure 3-2-2
5 4 3 2
- - -
REDG0
External Interrupt 0 Control Register (IRQ0ICR : x'03FE2', R/W)
1 0
(At reset : 0 0 0 - - - 0 0)
IRQ0IE IRQ0IR
IRQ0IR
IRQ0IE
REDG0
IRQ0
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for interrupt
request.
Chapter 3 Interrupts
External interrupt
request flag
0 No interrupt request
1 Interrupt request generated
External interrupt
enable flag
0 Disable interrupt
1 Enable interrupt
External interrupt active
edge flag
0 Falling edge
1 Rising edge
Interrupt level flag
IRQ0
for external interrupt
LV0
Control Registers
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