Overview; Block Diagram - Panasonic F77G User Manual

Microcomputer mn101c series

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Chapter 9 Watchdog Timer

Overview

This LSI has a watchdog timer. This timer is used to detect software processing errors. It is controlled by

the watchdog timer control register (WDCTR). And, once an overflow of watchdog timer is generated, a

watchdog interrupt (WDIRQ) is generated. If the watchdog interrupt is generated twice, consecutively, it

is regarded to be an indication that the software cannot execute in the intended sequence; thus, a

system reset is initiated by the hardware.

Watchdog Timer Block Diagram

The watchdog timer is also used as a timer to count the oscillation stabilization wait time. This is used as

a watchdog timer except at recovering from STOP mode and at reset releasing.

The watchdog timer is initialized at reset or at STOP mode, and counts system clock (fs) as a clock

source from the initial value (x'0000'). The oscillation stabilization wait time is set by the oscillation

stabilization control register (DLYCTR). After the oscillation stabilization wait, counting is continued as a

watchdog timer.

Figure 9-1-1

Block Diagram (Watchdog Timer)

2-8. Reset ]

internal reset release

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