Panasonic F77G User Manual page 123

Timer 7 Compare Register 2-match Interrupt Control Register (TOC2ICR)
The timer 7 compare register 2-match interrupt control register (TOC2ICR) controls interrupt level of
timer 7 compare register 2-match interrupt , interrupt enable flag and interrupt request. Interrupt control
register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
7 6
T7OC2 T7OC2
T7OC2ICR
LV1 LV0
Figure 3-2-17 Timer 7 Compare Register 2-match Interrupt Control Register
5 4 3 2
- - - -
(TMOC2ICR : x'03FF2', R/W)
1 0
T7OC2 T7OC2
(At reset : 0 0 - - - - 0 0)
IE IR
T7OC2IR
0
1
T7OC2IE
0
1
T7OC2
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Chapter 3 Interrupts
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
T7OC2
Interrupt level flag
LV0
Control Registers
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