Panasonic F77G User Manual page 89

[Setup for the second correction]
Set the head address of the program to be
corrected at second to the ROM correction address 1
setting register (RC1AP).
RC1APL = x'FD'
RC1APM = x'08'
RC1APH = x'01'
Set the internal RAM address x'06BC' that stored the
second correct program to the RC vector table address
(RC1V(L), RC1V(H).
RC1V(L) = x'BC'
RC1V(H) = x'06'
(STEP 3) Set the bit 0 (RC0EN) and the bit 1 (RC1EN) of the ROM correction control register
(RCCTR) to "1".
After the main program is started, the instruction fetched address and the set address
to the ROM correction address setting register (RCnAP) are always compared, then
once they are matched program counter indirectly branches to the address in RAM
area, that are stored to the RC vector table (RCnV).
The correction program in RAM area is executed.
Program counter recovers to the program in ROM area.
The second program to be corrected (internal ROM)
The head address of the correction
(the set value of RC1AP)
Address
Data
108FC 85
108FD A011
108FF 58
10900 EC1
10901_ A081
The address for recover
The second correct program (internal RAM)
The head address of the correction program
(the set value of RC1V)
Address
Data
006BC A041
006BE 58
006BF 3920090
The address for recover
ROM Correction
Chapter 2 CPU Basics
sub d1, d1
mov 11, d0
mov d0, (a0)
addw 1, a0
mov _Msyscom_edge, 0
mov 14, d0
mov d0, (a0)
jmp 10900
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