Panasonic F77G User Manual page 78

Chapter 2 CPU Basics
.
High-frequency
.
Low-frequency
OSCSEL1
On clock switching, set each flag of OSCDBL, OSCSEL, SOSCSEL and OSC0, individually.
Even if those flags are mapped on the same special functions register, set twice.
Set the OSC0 flag to "0" (NORMAL mode) before switching of division factor for
low-frequency input.
Set the division factor in SLOW mode only to 1 to 4 division and do not set other values.
II - 26
Clock Switching
4
.
fosc
2
.
1
fx
0
SOSC2DS
Figure 2-5-3
OSCSEL1 OSCSEL0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Figure 2-5-4 Setting Division Factor at NORMAL mode
by combination of OSCSEL and OSCDBL
OSCSEL0 SOSCDBL
0 0
0 0
0 0
0 0
0 1
Figure 2-5-5 Setting Division Factor at SLOW mode
by combination of OSCSEL and SOSC2DS
11
0
2
0
11
1
1
OSCDBL
OSC0
2
0
1
SOSCDBL
Clock Switching Circuit
Division factor for
OSCDBL
High-frequency (OSC) Input
(NORMAL mode)
0
1
0
1
0
1
0
1
SOSC2DS
Low-frequency (XI / XO) Input
0 0
0 1
1 0
1 1
1 0
CPU
. .
00
4
01
16
.
1*
OSCSEL[1:0]
2
1
8
4
32
16
64
64
Division factor for
(SLOW mode)
2
4
1
2
4
System Clock
fs