Clock Switching - Panasonic F77G User Manual

2-5

Clock Switching

This LSI can select the best operation clock for system by switching clock cycle division factor by
program. Division factor is determined by both flags of the CPU mode control register (CPUM) and the
Oscillator frequency control register (OSCMD). At the highest-frequency, CPU can be operated in the
same clock cycle to the external clock hence providing wider operating frequency range.
7 6
OSCMD
- -
Figure 2-5-1
7 6
CPUM
SOSCDBL
OSCSEL1 OSCSEL0 OSCDBL
Figure 2-5-2
5 4 3 2
- - - -
Oscillator Frequency Control Register (OSCMD : x'03F2D', R/W)
5 4 3 2
STOP HALT
CPU Mode Control Register (CPUM : x'03F00', R/W)
1
0
( At reset : - - - - - - 0 0 )
SOSC2DS Reserved
Reserved
SOSC2DS
0
1
1
0
( At reset : 0 0 0 0 0 0 0 0 )
OSC1 OSC0
OSCDBL
0
1
OSCSEL1
0
0
1
1
SOSCDBL
0
1
Chapter 2 CPU Basics
Set "0", always.
Low-frequency Clock
Standard (Input the oscillation clock cycle)
Divided (Input the oscillation clock cycle
divided by 2)
Internal System Clock
Standard (Input the oscillation clock cycle
divided by 2)
2x-speed (Input the oscillation clock cycle)
Division factor
OSCSEL0
NORMAL mode
0 1
1 4
0 16
1 64
Low Speed Oscillation Clock
Standard (Input the oscillation clock cycle
divided by 2)
2x-speed (Input the oscillation clock cycle)
Clock Switching
SLOW mode
1
4
16
16
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