Panasonic F77G User Manual page 131

ATC 1 Interrupt Control Register (ATC1ICR)
The ATC 1 interrupt control register (ATC1ICR) controls interrupt level of ATC 1 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
7 6
ATC1 ATC1
ATC1ICR
LV0
LV1
Figure 3-2-26
5 4 3 2
- - - -
ATC1 Interrupt Control Register (ATC1ICR : x'03FFC', R/W)
1 0
(At reset : 0 0 - - - - 0 0)
ATC1IE ATC1IR
ATC1IR
0
1
ATC1IE
0
1
ATC1
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Chapter 3 Interrupts
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
ATC1
Interrupt level flag
LV0
Control Registers
III - 37