Peripheral Functions; Functions - Panasonic F77G User Manual

3-1-1

Functions

Interrupt type
Vector number
Table address
Starting address
Interrupt level
Interrupt factor
Generated operation
Accept operation
Machine cycles until
acceptance
PSW status after acceptance
Table 3-1-1 Interrupt Functions
Reset (interrupt)
0
x'04000'
-
External RST pin input
Direct input to CPU core
Always accepts
12
All flags are cleared
to "0".
Non-maskable interrupt
1
x'04004'
Address specified by vector address
-
Errors detection,
PI interrupt
Input to CPU core from
non-maskable interrupt
control register (NMICR)
Always accepts
12
The interrupt mask level
flag in PSW is cleared
to "00".
Chapter 3 Interrupts
Maskable interrupt
2 to 28
x'04008' to x'04070'
Level 0 to 2
(set by software)
External pin input
Internal peripheral
function
Input interrupt request
level set in interrupt level flag
(xxxL Vn) of maskable
interrupt control register
(xxxICR) to CPU core.
Acceptance only by the
interrupt control of the register
(xxxICR) and the interrupt
mask level in PSW.
12
Values of the interrupt level
flag (xxxLVn) are set to the
interrupt mask level (masking
all interrupt requests with the
same or the lower priority.)
III - 3
Overview
3