Panasonic F77G User Manual page 121

Time Base Interrupt Control Register (TBICR)
The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
7 6
TB TB
TBICR
LV1 LV0
Figure 3-2-15
5 4 3 2
- - - -
Time Base Interrupt Control Register (TBICR : x'03FF0', R/W)
1 0
(At reset : 0 0 - - - - 0 0)
TBIE TBIR
TBIR
0
1
TBIE
0
1
TB
LV1
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
Chapter 3 Interrupts
Interrupt request flag
No interrupt request
Interrupt request generated
Interrupt enable flag
Disable interrupt
Enable interrupt
TB
Interrupt level flag
LV0
Control Registers
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