Performance Monitor Global Control Register (Pmgc) - Freescale Semiconductor MSC8144E Reference Manual

Debugging, Profiling, and Performance Monitoring

25.3.2.1 Performance Monitor Global Control Register (PMGC)

PMGCR
Bit 31 30 29
FAC PMIE FCECE
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
PMGC globally configures the PMC operation. Table 25-42 defines the PMGC bit fields.
Name Reset
FAC 0 Freeze All Counters
31 Enables or freezes all counters. This bit is set by hardware when a
performance monitor interrupt occurs and the FCECE bit is set.
PMIE 0 Performance Monitor Interrupt Enable
30 Enables/disables the performance monitor interrupt. When enabled,
the interrupt is asserted when a PMC overflows.
FCECE 0 Freeze Counters on Enabled Condition or Event
29 Determines whether a PMC can continue increment if permitted by
other control bits, or freezes when an enabled condition or event
occurs.
— 0 Reserved. Write to zero for future compatibility.
28–0
25-80
Performance Monitor Global Control Register
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
Table 25-42. PMGC Bit Descriptions
Description
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
R/W
0 0 0 0
8 7 6 5
—
R/W
0 0 0 0
Offset 0x00
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
Settings
0 PMCs increment if
permitted by other
control bits
1 PMCs do not
increment.
0 Interrupts disabled.
1 Interrupts enabled.
0 PMCs increment.
1 PMCs freeze when
the enabled
condition or event
occurs.
Freescale Semiconductor
16
0
0
0