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Note
As outlined in
MC68xx060 processor differ from those of the MC68xx040 used
on MVME162P4 series boards. Application software must take
these differences into account.
No-VMEbus-Interface Option
In support of possible future configurations in which the MVME172P4
might be offered as an embedded controller without the VMEbus interface,
certain logic in the VMEchip2 has been duplicated in the Petra chip. (For
the location of the overlapping logic, refer to Chapter 1 in the
MVME1X2P4 VME Embedded Controller Programmer's Reference
Guide.) As long as the VMEchip2 ASIC is present, the redundant logic is
inhibited in the Petra chip. The enabling signals for these functions are
controlled by software and Petra chip hardware initialization.
Memory Options
The following memory options are available on the different versions of
MVME172P4 boards.
DRAM
MVME172P4 boards are built with 16MB synchronous DRAM
(SDRAM). Depending on build options chosen at the time of manufacture,
various versions of the MVME172P4 have the SDRAM configured to
model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB,
8MB, or 16MB of ECC-protected DRAM.
The SDRAM memory array itself is always a single-bit error correcting
and multi-bit error detection memory, irrespective of which interface
model you use to access the SDRAM. When the MC2 (parity) memory
controller interface is used to access the SDRAM, single-bit errors are
undetectable to users and multi-bit errors are defined to be parity errors.
Firmware will initialize the memory controller to maintain backward
compatibility with MVME172FX or -LX products. If the Petra ASIC is
supporting MVME172FX functionality, the parity memory controller
model will be enabled by default. If the Petra ASIC is supporting
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Table
1-4, the snoop capabilities of the
Functional Description
4-7
4
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