Usb2.0 Debug Port Registers - AMD SB600 Technical Reference Manual

UTMI Control – RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h]
Field Name Bits
VBusy 17
Reserved 31:18
BIST Control / Loopback Test – RW - 32 bits - [EOR_Reg : EHCI_EOR + 98h]
Field Name Bits
Reserved 7:0
Enable Loop Back 8
test
Loopback Test 9
Status
Loopback Test 10
Done
Reserved 31:11
EOR MISC Control – RW - 32 bits - [EOR_Reg : EHCI_EOR + 9Ch]
Field Name Bits
Reserved 11:0
EHCI Power 12
Saving Enable
Reserved 31:13
USB Common PHY Calibration – RW - 32 bits - [EOR_Reg: EHCI_EOR + A0h]
Field Name Bits
ComCalBus 6:0
Reserved 7
NewCalBus 15:8
UsbCommonCalib 16
ration
AddToCommonCa 17
libration
Reserved 31:18
Note:
1. The equation for calibration resistor is as follows: Rcal = 1/ [1/59.4 + CalValue/(1.05*3.8k ohm)], where the
CalValue is the final 7 bits of calibration setting send to PHY.
2. The total termination resistance value for HS USB D+/D- should include another 5 ohm resistance from FS
driver.
2.2.3.4

USB2.0 Debug Port Registers

This block of registers is memory-mapped. The base offset, Dbase, is directly defined in DBUG_PRT
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Default
0b RO – To block software write to [16:8] when port router is updating the
field.
Reserved
Default
00h Reserved
0b Enable external USB Port Loop back test.
The Loop Back test is to set one port to TX mode (Test Packet mode)
and one port in RX mode (Test SE0_NAK). Please reference to
PORTSCx[19:16] control the port into TX or RX mode.
0b Read Only.
Loop back status.
0: CRC Error on Loop Back Receiving Data
1: Good CRC on Loop Back Receiving data
0b Read Only.
Indicate Loop back test done.
00000h
Default
000h Reserved
0b Enable power saving clock gating. When enabled, dynamic clock gating
is enabled when EHCI is not at operational mode. The clock goes to all
memory module will be gated off, and the internal bus clock also gets
gated off unless the connection interrupt is detected.
00000h Reserved
Default
xx Enables power saving clock gating (this was original at bit-31). When
enabled, dynamic clock gating is enabled when EHCI is not at
operational mode. The clock goes to all memory module will be gated
off, The blink clock also is gated off unless the connection interrupt is
detected.
0b Reserved
00h New calibration bus signed value. Bit-15 is the signed bit.
0b If set, the PHY's calibration value in bit[6:0] is returned to the PHY ports.
If clear, the value after adjustment is returned to the PHY ports.
0b If set, the signed NewCalBus is added to the ComCalBus and returned
to the PHY ports. Any overflow is clamped to all ones. Any underflow is
clamped to all zeros.
If clear, the NewCalBus (bit-14:8) replaces the ComCalBus and returns
to the PHY ports.
0000h Reserved
Description
Description
Description
Description
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary Page 92