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Pin Name
Multi-Function
(*Note 1)
Selection
GEVENT2/
PM IO
THRMTRIP#
Reg68h[Bit 3]
/SMBALERT
0: GEVENT2
#
1: THRMTRIP#
GEVENT3/
*Note 5
LPC_PME#
GEVENT4/
*Note 5
PCI_PME#
GEVENT5/
SMBus
S3_STATE
Reg64h[Bit 8]
=1 to enable
GPE
*Note 4
GEVENT6/
*Note 5
USB_OC6#
GEVENT7/
*Note 5
USB_OC7#
GEVENT8/
PM IO
WAKE#
Reg84h[Bit 0]
0: GEVENT8
1: WAKE#
PM IO
Reg84h[Bit 1]=1
and SMBus Reg
64h[Bit 19]=1 to
enable GPE
GPM0/
SMBus
USB_OC0#
Reg64h[Bit 23]
=1 to enable
GPE
GPM1/
SMBus
USB_OC1#
Reg64h[Bit 23]
=1 to enable
GPE
GPM2/
SMBus
USB_OC2#
Reg64h[Bit 23]
=1 to enable
GPE
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Configure Bit
Trigger Configure
00 – SCI or SMI#
0–Falling edge
01 – SMI#
1–Rising edge
10 – SMI#
followed by SCI
11 - IRQ13
PM IO
PM IO
Reg30h[Bit5:4]
Reg36h[Bit 2]
PM IO
PM IO
Reg30h[Bit7:6]
Reg36h[Bit3]
PM IO
PM IO
Reg31h[Bit1:0]
Reg36h[Bit4]
PM IO
PM IO
Reg31h[Bit3:2]
Reg36h[Bit 5]
PM IO
PM IO
Reg31h[Bit5:4]
Reg36h[Bit 6]
PM IO
PM IO
Reg31h[Bit7:6]
Reg36h[Bit 7]
PM IO
PM IO
Reg34h[Bit1:0]
Reg38h[Bit 0]
PM IO
PM IO
Reg32h[Bit7:6]
Reg37h[Bit 3]
PM IO
PM IO
Reg33h[Bit1:0]
Reg37h[Bit 4]
PM IO
PM IO
Reg33h[Bit3:2]
Reg37h[Bit 5]
Enable
Status
ACPI Event
(Write 1 to ACPI
GPE00h Bit to
Clear)
ACPI
PM IO
GPE04h[Bit 2]
Reg39h[Bit 2]
or ACPI
GPE00h[Bit 2]
ACPI
PM IO
GPE04h[Bit3]
Reg39h[Bit3]
or ACPI
GPE00h[Bit3]
ACPI
PM IO
GPE04h[Bit4]
Reg39h[Bit4]
or ACPI
GPE00h[Bit4]
ACPI
PM IO
GPE04h[Bit 5]
Reg39h[Bit 5]
or ACPI
GPE00h[Bit 5]
ACPI
PM IO
GPE04h[Bit 6]
Reg39h[Bit 6]
or ACPI
GPE00h[Bit 6]
ACPI
PM IO
GPE04h[Bit 7]
Reg39h[Bit 7]
or ACPI
GPE00h[Bit 7]
ACPI
PM IO
GPE04h[Bit24]
Reg3Bh[Bit 0]
or ACPI
GPE00h[Bit24]
ACPI
PM IO
GPE04h[Bit19]
Reg3Ah[Bit 3]
or ACPI
GPE00h[Bit19]
ACPI
PM IO
GPE04h[Bit20]
Reg3Ah[Bit 4]
or ACPI
GPE00h[Bit20]
ACPI
PM IO
GPE04h[Bit21]
Reg3Ah[Bit 5]
or ACPI
GPE00h[Bit21]
GEVENT/GPE/GPM/ExtEvent
Proprietary
Power
Domain
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
Page 284
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