AMD SB600 Technical Reference Manual page 275

Field Name
Read Size
Read Size Adjustment
Read Line Size
Read Line Adjustment
Read Multiple Size
Read Multiple
Adjustment
Prefetch Size Lower
Limit
Reserved
Prefetch Size Upper
Limit
Reserved
Prefetch Size Mlt
Enable
Reserved
The fields in this register are effective only when prefetch is enabled (reg0x64[7]=1).
Field Name
Downstream Config
Cycle Flush Enable
Downstream Write
Cycle Flush Enable
Downstream Read
Cycle Flush Enable
Prefetch Buffer Timeout
Enable
AB Masking Prefetch
Request Enable
AB Masking Non-
prefetch Request
Enable
Downstream Cycle
Flush Control
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Prefetch Size Control - 32 bits - [PCI_Reg: 60h]
Bits Default
2:0 2h If prefetch function is enabled, this defines the number of
initial prefetch cachelines for a PCI READ command
3 1b When set, PCIBridge will adjust the prefetch size for READ
automatically. If this bit is 0, then the prefetch size is always
defined by bits [2:0]
6:4 4h If prefetch function is enabled, this defines the number of
initial prefetch cachelines for a PCI READLINE command
7 1b When set, PCIBridge will adjust the prefetch size for
READ_LINE automatically. If this bit is 0, then the prefetch
size is always defined by bits [6:4]
10:8 6h If prefetch function is enabled, this defines the number of
initial prefetch cachelines for a PCI READ_MULTIPLE
command
11 1b When set, PCIBridge will adjust the prefetch size for
READ_MULTIPLE automatically. If this bit is 0, then the
prefetch size is always defined by bits [10:8]
14:12 0h The lower limit of the adjusted prefetch size.
15 0b
18:16 7h The upper limit of the adjusted prefetch size.
19 0b
20 1b This also controls how PCIBridge adjusts the auto-prefetch
size. When set, PCIBridge will only adjust the prefetch size
if it knows it does not have enough or has too much data in
the prefetch buffer. Recommendation is to always set this
bit.
31:21 0h
Misc Control Register - 32 bits - [PCI_Reg: 64h]
Bits Default
0 0h When this bit is 1, any downstream config cycle will flush all
the upstream read prefetch buffers.
1 1h When this bit is 1, any downstream non-config write cycle
will flush all the upstream read prefetch buffers.
2 0h When this bit is 1, any downstream non-config read cycle
will flush all the upstream read prefetch buffers.
3 1h When this bit is 1, upstream read prefetch buffer timeout
mechanism is enabled. If data stay in a buffer longer than
the time specified in Prefetch Timeout Limit (Reg5Ch), the
buffer will be flushed.
4 1h The purpose of this is to improve the internal bus efficiency
and the recommendation is to have it set to 1
5 1h The purpose of this is to improve the internal bus efficiency
and the recommendation is to have it set to 1
6 0h 0—If a downstream cycle is qualified to flush upstream
prefetch read buffer (depending on bit[2:0] in this register),
the flush happens when the cycle is sent out onto PCI bus
with at least one data phase..
1—If a downstream cycle is qualified to flush upstream
prefetch read buffer (depending on bit[2:0] in this register),
the flush happens as soon as the cycle arrives at PCI bus.
Description
Description
Host PCI Bridge Registers (Device 20, Function 4)
Proprietary Page 275