AMD SB600 Technical Reference Manual page 103

Field Name
DmaBurstLimit
DmaLimitEnable
DmaLimit register
Field Name
DmaPrefetchEnable
Reserved
DmaPrefetchEnable register
ISA Address Decode Control Register #1- RW - 8 bits - [PCI_Reg: 48h]
Field Name
Window 0
Window 1
Window 2
Window 3
Reserved
ISA Address Decode Control Register #1: This register defines the enable bits for four memory segments. If the
enable bit is set to 1, an ISA master or DMA access to the memory segment associated with that bit is forwarded to
the internal bus. The SB600 does not have any ISA master, because the bus is internal; however, it may affect
DMA transfers with the LPC module. Software should set all these bits to 1's.
ISA Address Decode Control Register #2- RW - 8 bits - [PCI_Reg: 49h]
Field Name
Window 0
Window 1
Window 2
Window 3
Window 4
Window 5
Window 6
Window 7
ISA Address Decode Control Register #1: This register defines the PCI enable bits for four memory segments. If
the enable bit is set to 1, an ISA master or DMA access to the memory segment associated with that bit is forward
to the internal bus. The SB600 does not have any ISA master, because the bus is internal; however, it may affect
the DMA transfers with the LPC module. Software should set all these bits to 1's.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
DmaLimit- RW - 8 bits - [PCI_Reg: 42h]
Bits Default
6:0 00h Enables the amount of burst data the legacy DMA engine can
sustain before it should give up the internal bus.
7 0h This is another enhancement to the legacy DMA engine. In
the original design, certain DMA request (such as Infrared) will
cause the legacy DMA engine to dominate the internal bus for
a very long time (up to 512 bytes) and thereby causing long
latency for other devices. Setting this bit will cause the legacy
DMA engine to limit its transfer per burst based on bits [6:0]
DmaPrefetchEnable RW - 8 bits - [PCI_Reg: 43h]
Bits Default
0 1b Legacy read DMA prefetch function enable.
1 – Enable
0 – Disable
When set, the DMA engine will keep the data inside the FIFO,
even though the requesting device has deasserted the DMA
request. When the device requests data again, the DMA
engine will have data available instead of having to fetch data
from the memory again. Note this enhancement only applies to
channel 0, 1, 2, and 3. It has no effect on channel 5, 6, or 7
7:1 00h
Bits Default
0 1b 896K to 960K PCI enable
1 1b 640K to 768K PCI enable
2 1b 512K to 640K PCI enable
3 1b 0K to 512K PCI enable
7:4 0h
Bits Default
0 1b C0000h to C3FFFh
1 1b C4000h to C7FFFh
2 1b C8000h to CBFFFh
3 1b CC000h to CFFFFh
4 1b D0000h to D3FFFh
5 1b D4000h to D7FFFh
6 1b D8000h to DBFFFh
7 1b DC000h to DFFFFh
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 103