Smbus Registers - AMD SB600 Technical Reference Manual

2.3.2

SMBus Registers

Note: The SMBus registers are located at the IO memory space base address defined by PCI configuration
register 90-93h
Field Name
HostBusy
SMBusInterrupt
DeviceErr
BusCollision
Failed
Reserved
Field Name
SlaveBusy
SlaveInit
SlaveStatus
Shadow1Status
Shadow2Status
AlertStatus
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
SMBusStatus
SMBusSlaveStatus
SMBusControl
SMBusHostCmd
SMBusAddress
SMBusData0
SMBusData1
SMBusBlockData
SMBusSlaveControl
SMBusShadowCmd
SMBusSlaveEvent
SlaveData
SMBusTiming
SMBusStatus - RW - 8 bits - [SMBUS:00h]
Bits Default
0 0b This bit indicates the SMBus controller is in the process of
completing a command. When this bit is set, software should
not access any other SMBus registers [Read-only]
1 0b This bit is set by hardware to indicate the completion of the last
host command. This bit can be cleared by writing an 1 to it.
2 0b This bit is set by hardware to indicate an error of one of the
following: 1) illegal command field, 2) unclaimed cycle, 3) host
device time-out. This bit can be cleared by writing an 1 to it.
3 0b This bit is set by hardware to indicate SMBus transaction
collision; this bit can be cleared by writing an 1 to it.
4 0b This bit is set by hardware to indicate a failed bus transaction,
set when SMBusControl.Kill bit is set. This bit is cleared by
writing an 1 to it
7:5 000b
SMBusSlaveStatus - RW - 8 bits - [SMBUS:01h]
Bits Default
0 0b This bit indicates the SMBus controller slave interface is in the
process of receiving data. Software should not try to access
any other SMBus register when this bit is set. [Read-only]
1 0b Writing a 1 to this bit will initialize the slave. It is unnecessary to
write it back to 0. A read from it will always return a 0.
2 0b This bit is set by hardware to indicate a slave cycle event match
of the SMBus slave command and SMBus Slave Event match.
This bit can be cleared by writing an 1 to it.
3 0b This bit is set by hardware to indicate a slave cycle address
match of the SMB_Shadow1 port. This bit can be cleared by
writing a 1 to it.
4 0b This bit is set by hardware to indicate a slave cycle address
match of the SMB_Shadow2 port. This bit can be cleared by
writing a 1 to it.
5 0b This bit is set by hardware to indicate SMBALERT_ signal. This
function is not supported. [Read-only]
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Offset Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0A-0Bh
0C-0Dh
0Eh
Page 123