Thrmtrip/Talert; Thermal Trip - Thrmtrip; Temperature Alert - Talert; Table 4-6: Thrmtrip Pin - AMD SB600 Technical Reference Manual

4.3

THRMTRIP/TALERT

4.3.1 Thermal Trip – THRMTRIP
The thermal trip function is multiplexed on the GEVENT2 pin. The THRMTRIP status cannot be used to
generate SCI or SMI#.

Table 4-6: THRMTRIP Pin

Pin Name Enable THRMTRIP
THRMTRIP#/ PM IO Reg68h[Bit 3]=1
GEVENT2#/ in addition PM IO
SMBALERT# Reg55h[Bit 0]=1 to
enable shutdown
4.3.2 Temperature Alert – TALERT
The temperature alert function is multiplexed on the GPIO64 pin. It can be programmed to generate SMI#,
SCI, or IRQ13 through GPE. It can also be programmed to generate SMI# without using GPE.

Table 4-7: TALERT# through GPE

Pin Name TALERT# Enable
TALERT#/ AcpiGpe0Blk04[Bit 9]=1
GPIO64/
TEMPIN3

Table 4-8: TALERT# to generate SMI#

Pin Name TALERT# SMI# Enable
TALERT#/
IO C50h/C51h, index 03h
GPIO64/
[Bit 1]=1
TEMPIN3
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
THRMTRIP
Polarity
Control
PM IO PM IO
Reg67h[Bit 6] Reg54h[Bit 0]
0=Active Low
1=Active High
TAERLT# TALERT# Status
Polarity
Control
PM IO AcpiGpe0Blk00[Bit 9]
Reg67h[Bit 5]
0=Active Low
1=Active High
TAERLT# TALERT# Status
Polarity
Control
PM IO
IO C50h/C51h, index
Reg67h[Bit 5]
02h [Bit 0]
0=Active Low
1=Active High
Proprietary
THRMTRIP Status
TALERT# Outcome
Controlled by
PM I/O Reg3Ch[Bit3:2]:
00= ACPI Event (SCI or SMI#,
depending on SCI_EN bit)
01= SMI#
10= N/A
11= IRQ13
TALERT# Outcome
SMI#
THRMTRIP/TALERT
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