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AMD Geode SC3200 Data Book

AMD Geode SC3200 Data Book

Processor
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AMD Geode™ SC3200 Processor
Data Book
February 2007
Publication ID: 32581C
AMD Geode™ SC3200 Processor Data Book

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Summary of Contents for AMD Geode SC3200

  • Page 1 AMD Geode™ SC3200 Processor Data Book February 2007 Publication ID: 32581C AMD Geode™ SC3200 Processor Data Book...
  • Page 2 No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty,...

  • Page 3: Table Of Contents

    Legacy Functional Blocks ........... . 127 AMD Geode™ SC3200 Processor Data Book...
  • Page 4 Data Book Revision History ..........426 Contents AMD Geode™ SC3200 Processor Data Book...

  • Page 5: List Of Figures

    Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer ....315 AMD Geode™ SC3200 Processor Data Book 32581C List of Figures...
  • Page 6 ECP Reverse Mode Timing Diagram ......... . 409 List of Figures AMD Geode™ SC3200 Processor Data Book...
  • Page 7 BGU481 Package - Bottom View ..........424 AMD Geode™ SC3200 Processor Data Book...
  • Page 8 32581C List of Figures AMD Geode™ SC3200 Processor Data Book...

  • Page 9: List Of Tables

    Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map ....115 AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 10 F2BAR4: IDE Controller Support Registers Summary ......181 List of Tables AMD Geode™ SC3200 Processor Data Book...
  • Page 11 PCI Clock Parameters ........... . . 373 AMD Geode™ SC3200 Processor Data Book...
  • Page 12 Revision History ............426 List of Tables AMD Geode™ SC3200 Processor Data Book...

  • Page 13: General Description

    Overview General Description The AMD Geode™ SC3200 processor is a member of the AMD Geode family of fully integrated x86 system chips. The SC3200 processor includes: • The AMD Geode GX1 processor module combines advanced CPU performance with MMX™ support, fully...

  • Page 14: Features

    – AC97 codec event – UART2 RI# signal – Infrared (IR) event ■ General Purpose I/Os (GPIOs): — 27 multiplexed GPIO signals ■ Low Pin Count (LPC) Bus Interface: — Specification v1.0 compatible AMD Geode™ SC3200 Processor Data Book Overview...
  • Page 15 Serial Port (UART): — UART1, 16550A compatible (SIN, SOUT, BOUT pins), used for SmartCard interface — UART2, 16550A compatible — Enhanced UART with fast Infrared (IR) AMD Geode™ SC3200 Processor Data Book 32581C Other Features ■ High-Resolution Timer: — 32-Bit counter with 1 μs count interval ■...
  • Page 16 32581C Overview AMD Geode™ SC3200 Processor Data Book...

  • Page 17: Gx1 Module

    The GX1 processor (silicon revision 8.1.1) is the central module of the SC3200. For detailed information regarding the GX1 module, refer to the AMD Geode™ GX1 Proces- sor Data Book and the AMD Geode™ GX1 Processor Sili- con Revision 8.1.1 Specification Update documents.

  • Page 18: Table 2-1. Sc3200 Memory Controller Register Summary

    MC_DR_ACC. Memory Controller Dirty RAM Access Register MC_MEM_CNTRL1 (R/W) 100: ÷ 3.5 101: ÷ 4 110: ÷ 4.5 111: ÷ 5 Architecture Overview Reset Value 248C0040h 00000801h 41104110h 2A733225h 00000000h 00000000h 0000000xh Reset Value: 248C0040h AMD Geode™ SC3200 Processor Data Book...
  • Page 19 1: 2 Core clocks. FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO. 0: Disable. 1: Enable. AMD Geode™ SC3200 Processor Data Book MC_MEM_CNTRL2 (R/W) 100: Shift 2 core clocks 101: Shift 2.5 core clocks...
  • Page 20 1111: 16 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK AMD Geode™ SC3200 Processor Data Book Architecture Overview Reset Value: 41104110h Reset Value: 2A733225h...
  • Page 21 31:2 RSVD (Reserved). Write as 0. D (Dirty Bit). This bit is read/write accessible. V (Valid Bit). This bit is read/write accessible. AMD Geode™ SC3200 Processor Data Book 100: 4 CLK 110: 6 CLK 101: 5 CLK 111: 7 CLK...

  • Page 22: Video Processor Module

    Video Processor. For more information about the GX1 module’s interface to the Video Processor, see the “Display Controller” chapter in the AMD Geode™ GX1 Processor Data Book. Video Processor Module The Video Processor provides high resolution and graphics for a TFT/DSTN interface.

  • Page 23: Super I/O Module

    The SuperI/O (SIO) module is a PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals. AMD Geode™ SC3200 Processor Data Book 32581C The SIO module incorporates: two Serial Ports, an Infrared Communication Port that supports FIR, MIR, HP-SIR, Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284 Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-...
  • Page 24 32581C Architecture Overview AMD Geode™ SC3200 Processor Data Book...

  • Page 25: 3.0Signal Definitions

    Straps are not the default signal, shown with system signals for reader convenience. However, also listed in figure with the appropriate functional group. AMD Geode™ SC3200 Processor Data Book 3.0Signal Definitions separated by a plus sign (+). A slash (/) in a signal name means that the function is always enabled and available (i.e., cycle multiplexed).
  • Page 26 GNT1#+DID1 A[23:0]/AD[23:0] D[7:0]/AD[31:24] D[11:8]/C/BE[3:0]# Sub-ISA/PCI Bus D12/PAR Interface D13/TRDY# D14/IRDY# D15/STOP# BHE#/DEVSEL# ROMCS#/BOOT16 RD#+CLKSEL0 GPIO0+TRDE# GPIO32+LAD0 GPIO33+LAD1 GPIO34+LAD2 GPIO/LPC Bus GPIO35+LAD3 Interface GPIO36+LDRQ# GPIO39+SERIRQ TEST1+PLL6B TEST0+PLL2B Test and Measurement TEST2+PLL5B Interface GTEST TDP, TDN AMD Geode™ SC3200 Processor Data Book...

  • Page 27: Ball Assignments

    Pin Multiplexing Register (PMR). See Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 70 for a detailed description of this register. AMD Geode™ SC3200 Processor Data Book 32581C Table 3-1. Signal Definitions Legend Mnemonic...

  • Page 28: Figure 3-2. Bgu481 Ball Assignment Diagram

    MD28 MD50 MD49 MD54 MD53 MD21 DQM6 DQM2 MD55 MA8 DQM1 MD13 MA11 CS1# MD18 MD48 MD20 MD51 MD11 SDCKI MD19 MD22 MD17 MA5 MD15 MD14 MD12 SDCKO MD16 MD8 MD10 MD9 MA12 MD23 AMD Geode™ SC3200 Processor Data Book...

  • Page 29: Table 3-2. Bgu481 Ball Assignment - Sorted By Ball Number

    22.5 IOCS0# 22.5 TFTDCK 22.5 HSYNC PLL2 5, 2 14/14 TFTD13 F_AD7 14/14 AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name 5, 2 Cycle Multiplexed TFTD1 F_AD6 Strap (See Table 3- 5, 2 4 on page 44.)
  • Page 30 4 on page 44.) PMR[9] = 0 and PMR[4] = 0 22.5 PMR[9] = 0 and PMR[4] = 1 22.5 PMR[9] = 1 and PMR[4] = 1 22.5 PMR[6] = 0 PMR[6] = 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 31 F_AD5 14/14 14/14 TFTD9 F_AD3 14/14 14/14 TFTD6 F_AD0 14/14 INTB# 22.5 SSUSB AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name GPIO9 DCD2# PMR[23] = 0 and (PMR[27] = 0 and IDE_IOW1# FPCI_MON = 0) PMR[23] = 1 and...
  • Page 32 Diode WIRE Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed 22.5 PMR[28] = 0 PMR[28] = 1 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 22.5 Cycle Multiplexed 22.5 AMD Geode™ SC3200 Processor Data Book...
  • Page 33 22.5 22.5 VPD6 VPD5 VPD4 VPD3 AD13 C/BE1# 22.5 22.5 AD15 22.5 22.5 VPD2 VPD1 VPD0 AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name GPIO39 SERIRQ AD11 Cycle Multiplexed AD14 GPIO38/IRRX2 LPCPD# Cycle Multiplexed GPIO37 LFRAME# C/BE0#...
  • Page 34 PMR[7] = 1 Cycle Multiplexed PMR[24] = 0 PMR[24] = 1 Cycle Multiplexed AC97 Strap (See Table 3- STRP 4 on page 44.) AC97 Strap (See Table 3- STRP 4 on page 44.) PMR[25] = 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 35 Type CORE CORE CORE CORE CORE CORE CORE CORE IDE_ADDR2 TFTD4 CORE CORE AC97_RST# F_STOP# BIT_CLK F_TRDY# AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name SDATA_IN F_GNT0# IDE_DATA15 TFTD7 IDE_DATA14 TFTD17 IDE_DATA13 TFTD15 CORE CORE CORE CORE...
  • Page 36 PMR[24] = 0 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 PMR[24] = 0 PMR[24] = 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 37 MD55 AG31 POWER_EN X27O WIRE TEST0 PLL2B PWRBTN# GPWIO0 2/14 CLK32 POR# AH10 AH11 AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name AH12 WEA# AH13 PMR[24] = 0 AH14 PMR[24] = 1 AH15 PMR[24] = 0 MD34...
  • Page 38 SDATA_IN2 AL10 AL11 DQM0 PMR[6] = 0 AL12 CS0# PMR[6] =1 AL13 AL14 AL15 DQM4 AL16 MD38 AL17 MD39 AL18 AL19 Signal Definitions Buffer Power (PU/PD) Type Rail Configuration F3BAR0+Memory Offset 08h[21] = 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 39 AL24 AL25 MD10 AL26 AL27 AL28 MA12 MD23 AL29 AMD Geode™ SC3200 Processor Data Book Ball Rail Configuration Signal Name AL30 AL31 For Buffer Type definitions, refer to Table 9-10 "Buffer Types" on page 357. Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).

  • Page 40: Table 3-3. Bgu481 Ball Assignment - Sorted Alphabetically By Signal Name

    CASA# AJ12 CKEA AL22 CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 CS0# AL12 CS1# AH27 CTS2# AMD Geode™ SC3200 Processor Data Book Signal Definitions Signal Name Ball No. DCD2# DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# A9, N31 DOCR# DOCW# DPOS_PORT1...
  • Page 41 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2 GTEST GXCLK HSYNC IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 AMD Geode™ SC3200 Processor Data Book Signal Name Ball No. IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14...
  • Page 42 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SIN1 SIN2 SIN3 SLCT SLIN#/ASTRB# SMI_O SOUT1 SOUT2 SOUT3 AMD Geode™ SC3200 Processor Data Book Signal Definitions Signal Name Ball No. STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT TFTD0 A9, AD4 TFTD1 A20, AF1...
  • Page 43 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 PLL2 PLL3 AMD Geode™ SC3200 Processor Data Book Signal Name Ball No. (Total of 96) A1, A13, A16, A19, A31, B1, B7, B10, B14, B22, B24, B25, B30, C12, C14, C15, D7, D13, D19,...

  • Page 44: Strap Options

    Note: Accuracy of internal PU/PD resistors: 80K to 250K. Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC3200 Specifi- cation Update document. of 1.5 KΩ be placed on the balls listed in Table 3-4. The value of the resistor is important to ensure that the proper state is read during the power-up sequence.

  • Page 45: Multiplexing Configuration

    IDE_RST# IRQ14 Sub-ISA TRDE# AMD Geode™ SC3200 Processor Data Book system reset, the pull-up is present. This pull-up resistor can be disabled by writing Core Logic registers. The config- uration is without regard to the selected ball function. The above applies to all pins multiplexed with GPIO, except GPIO12, GPIO13, and GPIO16.

  • Page 46: Table 3-6. Three-Signal/Group Multiplexing

    PMR[14] = 1 and PMR[22] = Internal Test PMR[28] = 1 FPCI Monitoring FPCI_MON = 1 Internal Test PMR[29] = 1 Alternate2 Signal Configuration GPIO GPIO14 PMR[21] = 1 and PMR[2] = 1 GPIO15 FPCI Monitoring AMD Geode™ SC3200 Processor Data Book...
  • Page 47 The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and should not be used. These TFT outputs are reset to 0 by POR# if the TFT_PRSNT strap is pulled high or PMR[10] = 0. This relates to signals TFTD[17:0], TFTDE, TFTDCK. AMD Geode™ SC3200 Processor Data Book Alternate1 Signal...

  • Page 48: Table 3-7. Four-Signal/Group Multiplexing

    Signal Configuration IDE2 Internal Test PMR[17] = 0 SDTEST0 PMR[17] = 1 SDTEST4 PMR[8] = 1 PMR[8] = 1 PMR[18] = 0 SDTEST5 PMR[18] = 1 SDTEST2 PMR[8] = 1 PMR[8] = 1 SDTEST1 AMD Geode™ SC3200 Processor Data Book...

  • Page 49: Signal Descriptions

    BOOT16 LPC_ROM TFT_PRSNT FPCI_MON DID1 DID0 POR# AMD Geode™ SC3200 Processor Data Book Description Fast-PCI Clock Selects. These strap signals are used to set the internal Fast-PCI clock. 00 = 33.3 MHz 01 = 48 MHz 10 = 66.7 MHz 11 = 33.3 MHz...

  • Page 50: Memory Interface Signals

    SDRAM commands. CASA# is used with CS[1:0]#. Write Enable. RAS#, CAS#, WE# and CKE are encoded to support the different SDRAM commands. WEA# is used with CS[1:0]#. Signal Definitions IDE_DATA5 AMD Geode™ SC3200 Processor Data Book...
  • Page 51 VPD3 VPD2 VPD1 VPD0 VPCKIN AMD Geode™ SC3200 Processor Data Book Description Data Mask Control Bits. During memory read cycles, these outputs control whether SDRAM output buffers are driven on the MD bus or not. All DQM signals are asserted during read cycles.
  • Page 52 IDE_DATA4 GXCLK+TEST3 The TFT interface is muxed with the IDE interface or the Par- allel Port. See Table 3-5 on page 45 and Table 3-6 on page 46 for details. GPIO20+DOCCS# GPIO1+IOCS1# GPIO12 GPIO13 AMD Geode™ SC3200 Processor Data Book...

  • Page 53: Pci Bus Interface Signals

    INTA# INTB# INTC# INTD# AMD Geode™ SC3200 Processor Data Book Description PCI Clock. PCICLK provides timing for all transactions on the PCI bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge.
  • Page 54 On read cycles that cross cache line boundaries. This is conditional based upon the programming of GX1 module’s PCI Configuration Register, Index 41h[1]. This signal is internally connected to a pull-up resistor. Signal Definitions AMD Geode™ SC3200 Processor Data Book...
  • Page 55 Type LOCK# DEVSEL# PERR# SERR# AMD Geode™ SC3200 Processor Data Book Description Lock Operation. LOCK# indicates an atomic operation that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may pro- ceed to an address that is not currently locked (at least 16 bytes must be locked).
  • Page 56 Each of these signals is internally connected to a pull-up resistor. GNT0# must have a pull-up resistor of 1.5 KΩ and GNT1# must have a pull-up resistor of 1.5 KΩ. Signal Definitions DID1 (Strap) DID0 (Strap) AMD Geode™ SC3200 Processor Data Book...
  • Page 57 DOCCS# TRDE# IOR# IOW# DOCR# DOCW# IRQ9 IOCHRDY AMD Geode™ SC3200 Processor Data Book Type Description Address Lines Data Bus Byte High Enable. With A0, defines byte accessed for 16 bit wide bus cycles. I/O Chip Selects ROM or Flash ROM Chip Select DiskOnChip or NAND Flash Chip Select Transceiver Data Enable Control.
  • Page 58 GPIO32 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 TFTDCK TFTD4 TFTD2 TFTD3 The IDE interface is muxed with the TFT interface. See Table 3-5 on page 45 for details. TFTD10 GPIO6+DTR2#/ BOUT2+SDTEST5# TFTD9 GPIO9+DCD2#+ SDTEST2 TFTD5 TFTDE AMD Geode™ SC3200 Processor Data Book...
  • Page 59 DPOS_PORT3 DNEG_PORT3 A 15K ohm pull-down resistor is required on all ports (even if unused). AMD Geode™ SC3200 Processor Data Book Description I/O Ready Channels 0 and 1. When de-asserted, these signals extend the transfer cycle of any host register access if the required device is not ready to respond to the data transfer request.
  • Page 60 Note: If selected as DSR2# function but not used, tie DSR2# low. Signal Definitions SDTEST3 IRRX1 CLKSEL1 (Strap) CLKSEL2 (Strap) IRTX GPIO7+ IDE_DACK1# GPIO8+ IDE_DREQ1 GPIO18 GPIO6+IDE_IOR1# GPIO11+IRQ15 GPIO9+IDE_IOW1# +SDTEST2 GPIO10+ IDE_IORDY1 AMD Geode™ SC3200 Processor Data Book...
  • Page 61 BUSY/WAIT# ERR# INIT# SLCT SLIN#/ASTRB# AMD Geode™ SC3200 Processor Data Book Description Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port. Automatic Feed. When low, instructs the printer to auto- matically feed a line after printing each line. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit.
  • Page 62 GPIO38 is selected using PMR[14], and when AUX_IRRX bit in register IRCR2 of the IR module in internal SuperI/O is set. IR Transmit. IR serial output data. Signal Definitions TFTD17+ F_FRAME# SIN3 LPCPD# SOUT3 AMD Geode™ SC3200 Processor Data Book...
  • Page 63 SDATA_IN SDATA_IN2 SYNC AC97_CLK AC97_RST# PC_BEEP AMD Geode™ SC3200 Processor Data Book Description Audio Bit Clock. The serial bit clock from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low. Serial Data Output. This output transmits audio serial data to the codec.

  • Page 64: Power Management Interface Signals

    Suspend Power Plane Control 1 and 2. Control signal asserted during power management Suspend states. These signals are open-drain outputs. Thermal Event. Active low signal generated by external hardware indicating that the system temperature is too high. Signal Definitions AMD Geode™ SC3200 Processor Data Book...

  • Page 65: Gpio Interface Signals

    GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 AMD Geode™ SC3200 Processor Data Book Description GPIO Port 0. Each signal is configured independently as an input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. A debouncer and an interrupt can be enabled or masked for each of signals GPIO[00:01] and [06:15] indepen- dently.

  • Page 66: Jtag Interface Signals

    JTAG Test Mode Select. This signal has an internal weak pull-up resistor. Signal Definitions ACK#+TFTDE PD7+TFTD13 PD6+TFTD1 PD5+TFTD11 PD4+TFTD10 PD3+TFTD9 PD2+TFTD8 PD1+TFTD7 PD0+TFTD6 SLCT+TFTD15 PE+TFTD14 BUSY/WAIT#+ TFTD3 ERR#+TFTD4+ STB#/WRITE#+ TFTD17 SLIN#/ASTRB#+ TFTD16 AC97_RST# GPIO16+ PC_BEEP SDATA_IN BIT_CLK AFD#/DSTRB#+ TFTD2 INIT#+TFTD5+ AMD Geode™ SC3200 Processor Data Book...
  • Page 67 SDTEST5 SDTEST4 SDTEST3 SDTEST2 SDTEST1 SDTEST0 AMD Geode™ SC3200 Processor Data Book Description JTAG Test Reset. This signal has an internal weak pull- up resistor. For normal JTAG operation, this signal should be active at power-up. If the JTAG interface is not being used, this signal can be tied low.
  • Page 68 3.3V I/O Power Connections. Ground Connections. No Connections. These lines should be left disconnected. Connecting a pull-up/-down resistor or to an active signal could cause unexpected results and possible malfunctions. Signal Definitions to V is present. AMD Geode™ SC3200 Processor Data Book...

  • Page 69: 4.0General Configuration Block

    30h-33h 34h-37h 39h-3Bh 3Eh-3Fh AMD Geode™ SC3200 Processor Data Book 4.0General Configuration Block not have a register block in PCI configuration space (i.e., they do not appear to software as PCI registers). After system reset, the Base Address register is located at I/O address 02EAh.

  • Page 70: Multiplexing, Interrupt Selection, And Base Address Registers

    See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] See PMR[23] FPCI_MON = 1 and see PMR[0] FPCI_MON = 1 FPCI_MON = 1 FPCI_MON = 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 71 C24 / AC4 IDE_DREQ0 C25 / AD4 IDE_DACK0# A22 / AA1 IDE_RST# A25 / AD1 IDE_IORDY0 D25 / AF1 IRQ14 AMD Geode™ SC3200 Processor Data Book 32581C 1: GPIO and TFT Signals Name TFTD3 TFTD2 TFTD4 TFTD6 TFTD16 TFTD14 TFTD12...
  • Page 72 TFTD2 Note 2 None GPIO20 DOCCS# None GPIO1 IOCS1# PMR[29] = 0 FP_VDD_ON PMR[29] = 1 AMD Geode™ SC3200 Processor Data Book General Configuration Block Add’l Dependencies None None None None Note 1 Note 1 Note 1 Note 1 Note 1...
  • Page 73 GPIO38/IRRX2 AL8 / J31 GPIO39 IOCS1SEL (Select IOCS1). Selects ball functions for IOCS1# or GPIO1. Works in conjunction with PMR[23], see PMR[23] for definition. AMD Geode™ SC3200 Processor Data Book 1: GPIO Signals Add’l Dependencies Name PMR[2] = 0 GPIO14...
  • Page 74 None SOUT3 1: Audio Signal Add’l Dependencies Name FPCI_MON = 0 PC_BEEP FPCI_MON = 1 F_DEVSEL# AMD Geode™ SC3200 Processor Data Book General Configuration Block Add’l Dependencies None Add’l Dependencies PMR[4] = 1 PMR[4] = 0 Add’l Dependencies None None Add’l Dependencies...
  • Page 75 16-bit access to ROM in the Sub-ISA interface is enabled. MCR[14] = 1 inverts the meaning of this register. 0: 8-bit wide ROM. 1: 16-bit wide ROM. Reserved. Write as read. AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 76 Device Identification Number Register - ID (RO) This register identifies the device. SC3200 = 04h. Offset 3Dh This register identifies the device revision. See the AMD Geode™ SC3200 Specification Update document for value. Offset 3Eh-3Fh Configuration Base Address Register - CBA (RO) This register sets the base address of the Configuration block.

  • Page 77: Watchdog

    SUSPA# 32 KHz WDPRES POR# AMD Geode™ SC3200 Processor Data Book • The GX1 module’s internal SUSPA# signal is 1. • The GX1 module’s internal SUSPA# signal is 0 and the WD32KPD bit (Offset 02h[8]) is 0. The 32 KHz input clock is disabled, when: •...

  • Page 78: Table 4-3. Watchdog Registers

    Table 4-3. WATCHDOG Registers WATCHDOG Timeout Register - WDTO (R/W) 1000: 256 1100: 4096 1001: 512 1101: 8192 1010: 1024 1110: Reserved 1011: 2048 1111: Reserved General Configuration Block Reset Value: 0000h Reset Value: 0000h AMD Geode™ SC3200 Processor Data Book...

  • Page 79: High-Resolution Timer

    SUSPA# signal is 0 and the TM27MPD bit is 1. For more information about signal SUSPA# see Section 4.4.2.1 "Usage Hints" on page 79 and the AMD Geode™ GX1 Processor Data Book. The High-Resolution Timer function resides on the internal Fast-PCI bus and its registers are in General Configuration Block address space.

  • Page 80: Table 4-4. High-Resolution Timer Registers

    1: High-Resolution Timer interrupt is enabled. Offset 0Eh-0Fh TIMER Value Register - TMVALUE (RO) TIMER Status Register - TMSTS (R/W) Reserved - RSVD General Configuration Block Reset Value: xxxxxxxxh Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 81: Clock Generators And Plls

    PLL2 and PLL5. V PLL2 Figure 4-2. Clock Generation Block Diagram AMD Geode™ SC3200 Processor Data Book The clock generators are based on 32.768 KHz and 27.000 MHz crystal oscillators. The 32.768 KHz crystal oscillator is described in Section 5.5.2 "RTC Clock Generation" on page 103 (functional description of the RTC).

  • Page 82: Figure 4-3. Recommended Oscillator External Circuitry

    AT-cut or BT-cut 40 Ω 7 pF 10-20 pF User-defined 20 MΩ 100 Ω 3-24 pF 3-24 pF General Configuration Block To other modules Internal External X27I X27O Circuitry Tolerance 50 PPM or better AMD Geode™ SC3200 Processor Data Book...

  • Page 83: Table 4-6. Core Clock Frequency

    0110 66.67 1010 Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page 425. AMD Geode™ SC3200 Processor Data Book Table 4-6. Core Clock Frequency Internal Fast-PCI Clock Freq. (MHz) Multiplier Value 33.33...
  • Page 84 (Capture Video mode), the video clock is generated by the Display Controller. • If the video data is coming directly from the VIP block (Direct Video mode), the Video Clock is generated by the VIP block. AMD Geode™ SC3200 Processor Data Book...

  • Page 85: Table 4-8. Clock Generator Configuration

    MOC (MO Counter Value). Fvco = OSCCLK * MFBC / (MFFC * MOC) OSCCLK = 27 MHz AMD Geode™ SC3200 Processor Data Book Reserved - RSVD PLL Power Control Register - PPCR (R/W) Reserved - RSVD PLL3 Configuration Register - PLL3C (R/W)
  • Page 86 0100: Multiply by 4 0101: Multiply by 5 0110: Multiply by 6 0111: Multiply by 7 1000: Multiply by 8 1001: Multiply by 9 1010: Multiply by 10 Other: Reserved General Configuration Block Reset Value: Strapped Value AMD Geode™ SC3200 Processor Data Book...

  • Page 87: 5.0Superi/O Module

    Serial Port 2 System Wakeup Control Wakeup PWUREQ Events AMD Geode™ SC3200 Processor Data Book 5.0SuperI/O Module Outstanding Features • Full compatibility with ACPI Revision 1.0 requirements. • System Wakeup Control powered by V power-up request and a PME (power management...

  • Page 88: Features

    • Y2K Compliant Clock Sources • 48 MHz clock input • On-chip low frequency clock generator for wakeup • 32.768 KHz crystal with an internal frequency multiplier to generate all required internal frequencies AMD Geode™ SC3200 Processor Data Book SuperI/O Module...

  • Page 89: Module Architecture

    AB2D Real-Time Clock (RTC) Internal Signal AMD Geode™ SC3200 Processor Data Book The central configuration register set supports ACPI com- pliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Reg- isters, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft®.

  • Page 90: Configuration Structure / Access

    Configuration Register File SuperI/O Module Reference Page 96 Page 98 Page 99 Page 100 Page 101 Page 102 Page 100 SIO Configuration Registers Standard Logical Device Standard Registers Bank Special (Vendor-defined) Select Logical Device Configuration Registers AMD Geode™ SC3200 Processor Data Book...

  • Page 91: Address Decoding

    • When either a hardware or a software reset occurs: — The legacy devices are assigned with their legacy system resource allocation. — The AMD proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.

  • Page 92: Standard Configuration Registers

    DMA Channel Select 0 DMA Channel Select 1 Device Specific Logical Device Configuration 1 Device Specific Logical Device Configuration 2 Device Specific Logical Device Configuration 3 Device Specific Logical Device Configuration 4 SuperI/O Module AMD Geode™ SC3200 Processor Data Book...

  • Page 93: Table 5-3. Standard Configuration Registers

    The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. AMD Geode™ SC3200 Processor Data Book write to prevent the values of reserved bits from being changed during write.
  • Page 94 The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. Values 5-7 are reserved. Index F0h-FEh Special (vendor-defined) configuration options. DMA Channel Select 1 (R/W) Logical Device Configuration (R/W) SuperI/O Module AMD Geode™ SC3200 Processor Data Book...

  • Page 95: Table 5-4. Sio Control And Configuration Register Map

    SID. SIO ID SIOCF1. SIO Configuration 1 SIOCF2. SIO Configuration 2 SRID. SIO Revision ID RSVD. Reserved exclusively for AMD use. Table 5-5. SIO Control and Configuration Registers Description Index 20h Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.

  • Page 96: Table 5-6. Relevant Rtc Configuration Registers

    Real-Time Clock (RTC). Only the last registers (F0h-F3h) are described here (Table 5-7). See Table 5-3 "Standard Configuration Registers" on page 93 for descrip- tions of the other registers. AMD Geode™ SC3200 Processor Data Book SuperI/O Module Reset Value...

  • Page 97: Table 5-7. Rtc Configuration Registers

    Month Alarm Register Offset Register - MANAO (R/W) Reserved. Month Alarm Register Offset Value. Index F3h Century Register Offset Register - CENO (R/W) Reserved. Century Register Offset Value. AMD Geode™ SC3200 Processor Data Book Table 5-7. RTC Configuration Registers RAM Lock Register - RLR (R/W) 32581C...

  • Page 98: Table 5-8. Relevant Swc Registers

    The logical device registers are maintained, and all wakeup detection mechanisms are functional. described earlier in Table 5-3 "Standard Configuration Reg- isters" on page 93. Table 5-8. Relevant SWC Registers SuperI/O Module Reset Value AMD Geode™ SC3200 Processor Data Book...

  • Page 99: Table 5-9. Relevant Ircp/Sp3 Registers

    0: Disabled. (Default) 1: Enabled (when the device is inactive). AMD Geode™ SC3200 Processor Data Book Only the last register (F0h) is described here (Table 5-10). See Table 5-3 "Standard Configuration Registers" on page 93 for descriptions of the other registers listed.

  • Page 100: Table 5-11. Relevant Serial Ports 1 And 2 Registers

    Serial Ports 1 and 2. Only the last register (F0h) is described here (Table 5-12). See Table 5-3 "Standard Con- figuration Registers" on page 93 for descriptions of the oth- ers. AMD Geode™ SC3200 Processor Data Book SuperI/O Module Reset Value Port 1...

  • Page 101: Table 5-13. Relevant Acb1 And Acb2 Registers

    0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default) 1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. Reserved. AMD Geode™ SC3200 Processor Data Book ACB1 is designated as LDN 05h and ACB2 as LDN 06h. Table 5-13 lists the configuration registers which affect the ACCESS.bus ports.

  • Page 102: Table 5-15. Relevant Parallel Port Registers

    Parallel Port. Only the last register (F0h) is described here (Table 5-16). See Table 5-3 "Standard Configuration Regis- ters" on page 93 for descriptions of the others. Parallel Port Configuration Register (R/W) SuperI/O Module Reset Value Reset Value: F2h AMD Geode™ SC3200 Processor Data Book...

  • Page 103: Real-Time Clock (Rtc)

    (whether system is on or off). In systems where this is not the case, C1 and C2 should be different by 50% to assure an unbalanced circuit. AMD Geode™ SC3200 Processor Data Book These locations may be reassigned, in compliance with Plug and Play requirements.

  • Page 104: Figure 5-6. External Oscillator Connections

    (X32I) 3.3V square wave POWER = 30 KΩ 32.768 KHz Clock Generator = 30 KΩ = 0.1 μF Divider Chain 1 Hz Reset DV2 DV1 DV0 CRA Register Oscillator To other Enable modules X32O AMD Geode™ SC3200 Processor Data Book...
  • Page 105 This mecha- nism enables new time parameters to be loaded in the RTC. AMD Geode™ SC3200 Processor Data Book 32581C Method 2 Access the RTC registers after detection of an Update Ended interrupt.

  • Page 106: Figure 5-8. Power Supply Connections

    (μA) 2.4 3.0 3.6 = 25°C 3.0 3.3 3.6 Operation Mode AMD Geode™ SC3200 Processor Data Book and not...

  • Page 107: Table 5-18. System Power States

    To protect the RTC internal regis- ters from corruption, all inputs are automatically locked out. The lockout condition is asserted when V SBON AMD Geode™ SC3200 Processor Data Book Power-Up Detection When system power is restored after a power failure or power off state (V for a delay of 62 ms (minimum) to 125 ms (maximum) after the RTC switches from battery to system power.

  • Page 108: Figure 5-12. Interrupt/Status Timing

    128 bytes of battery-backed RAM (also called Extended RAM) may be accessed via a second pair of Index and Data registers. Access to the two RAMs may be locked. For details see Table 5-7 on page 97. SuperI/O Module AMD Geode™ SC3200 Processor Data Book...

  • Page 109: Table 5-19. Rtc Register Map

    Index 02h Minutes Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format. AMD Geode™ SC3200 Processor Data Book Note: Before attempting to perform any start-up proce- dures, read about bit 7 (VRT) of the CRD Register.
  • Page 110 SuperI/O Module Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: V Reset Type: Bit Specific Reset Type: Bit Specific AMD Geode™ SC3200 Processor Data Book...
  • Page 111 When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default) Index Programmable Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format. AMD Geode™ SC3200 Processor Data Book Table 5-20. RTC Registers (Continued) power-up reset only.

  • Page 112: Table 5-21. Divider Chain Control / Test Selection

    Rate (ms) Chain Output No interrupts 3.906250 7.812500 0.122070 0.244141 0.488281 0.976562 1.953125 3.906250 7.812500 15.625000 31.250000 62.500000 125.000000 250.000000 500.000000 Binary Format 01 to 0C (AM) 81 to 8C (PM) 00 to 17 AMD Geode™ SC3200 Processor Data Book...

  • Page 113: Table 5-24. Standard Ram Map

    The supercap capacitor in the range of 0.047- 0.47 F should supply the power during the battery replacement. AMD Geode™ SC3200 Processor Data Book 32581C 5.5.4 RTC General-Purpose RAM Map Table 5-24.

  • Page 114: System Wakeup Control (Swc)

    Table 5-26 lists the recommended time ranges limits for the different protocols and their applicable ranges. The values are represented in hexadecimal code where the units are of 0.1 ms. Low Limit High Limit SuperI/O Module Low Limit High Limit AMD Geode™ SC3200 Processor Data Book...

  • Page 115: Table 5-27. Banks 0 And 1 - Common Control And Status Register Map

    Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map Offset Type AMD Geode™ SC3200 Processor Data Book • Bank 0 holds reserved registers. • Bank 1 holds the CEIR Control Registers. The active bank is selected through the Configuration Bank Select field (bits [1:0]) in the Wakeup Configuration Regis- ter (WKCFG).

  • Page 116: Table 5-29. Banks 0 And 1 - Common Control And Status Registers

    Detected wakeup events that are enabled issue a power-up request the or software reset. It enables access to CEIR registers. SuperI/O Module Reset Value: 00h Reset Value: 03h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 117: Table 5-30. Bank 1 - Ceir Wakeup Configuration And Control Registers

    Bank 1, Offset 09h This register is set to 14h on power-up of V Reserved. CEIR Pulse Change, Range 0, High Limit. AMD Geode™ SC3200 Processor Data Book CEIR Wakeup Control Register - IRWCR (R/W) or software reset. Reserved CEIR Wakeup Address Register - IRWAD (R/W) or software reset.
  • Page 118 CEIR Wakeup Range 3 Registers IRWTR3L Register (R/W) or software reset. IRWTR3H Register (R/W) or software reset. SuperI/O Module Reset Value: 07h Reset Value: 0Bh Reset Value: 50h Reset Value: 64h Reset Value: 28h Reset Value: 32h AMD Geode™ SC3200 Processor Data Book...

  • Page 119: Access.bus Interface

    (8 bits), an Acknowledge signal must follow. The following sections provide further details of this process. AMD Geode™ SC3200 Processor Data Book 32581C During each clock cycle, the slave can stall the master while it handles the previous data or prepares new data.

  • Page 120: Figure 5-15. Access.bus Data Transaction

    Clock Line Held Byte Complete Interrupt Within Low by Receiver Receiver While Interrupt is Serviced 2 3 - 6 SuperI/O Module Stop Condition Transmitter Stays Off Bus During Acknowledge Clock Acknowledge Signal From Receiver AMD Geode™ SC3200 Processor Data Book...

  • Page 121: Master Mode

    1 - 7 Start Address R/W ACK Condition Figure 5-17. A Complete ACCESS.bus Data Transaction AMD Geode™ SC3200 Processor Data Book 5.7.6 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle.
  • Page 122 Follow the address send sequence, as described pre- viously in "Sending the Address Byte". If the ACB was awaiting handling due to ACBST[3] = 1, clear it only after writing the requested address and direction to ACBSDA. AMD Geode™ SC3200 Processor Data Book SuperI/O Module...
  • Page 123 ACBCST[2] and ACBST[2] are set. If ACBST[0] = 1 (i.e., slave transmit mode) ACBST[6] is set to indicate that the buffer is empty. AMD Geode™ SC3200 Processor Data Book 32581C If ACBCTL1[2] is set, an interrupt is generated if both ACBCTL1[2] and ACBCTL16 are set.

  • Page 124: Table 5-31. Acb Register Map

    ACBADDR. ACB Own Address ACBCTL2. ACB Control 2 Table 5-32. ACB Registers ACB Serial Data Register - ACBSDA (R/W) ACB Status Register - ACBST (R/W) SuperI/O Module Reset Value Reset Value: xxh Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 125 GCMEN (Global Call Match Enable). 0: Global call match disabled. 1: Global call match enabled. AMD Geode™ SC3200 Processor Data Book Table 5-32. ACB Registers (Continued) ACB Control Status Register - ACBCST (R/W) ACB Control Register 1 - ACBCTL1 (R/W)
  • Page 126 0: ACB is disabled, ACBCTL1, ACBST and ACBCST registers are cleared, and clocks are halted. 1: ACB is enabled. Table 5-32. ACB Registers (Continued) ACB Own Address Register - ACBADDR (R/W) ACB Control Register 2 - ACBCTL2 (R/W) SuperI/O Module Reset Value: xxh Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 127: Legacy Functional Blocks

    405h Table 5-34. Parallel Port Register Map for Second Level Offset Second Level Offset Type AMD Geode™ SC3200 Processor Data Book 5.8.1 Parallel Port The Parallel Port supports all IEEE1284 standard commu- nication modes: Compatibility (known also as Standard or...

  • Page 128: Table 5-35. Parallel Port Bit Map For First Level Offset

    FIFO FIFO rupt Ser- Full Empty vice Second Level Offset RSVD RSVD EPP Time- out Inter- rupt Mask RSVD RSVD PP DMA Request Active Time PE Inter- ECP DMA Channel nal PU or Number AMD Geode™ SC3200 Processor Data Book...

  • Page 129: Figure 5-18. Uart Mode Register Bank Architecture

    Banks 0 through 3. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38. AMD Geode™ SC3200 Processor Data Book Bank 1 Bank 0 Offset 07h...

  • Page 130: Table 5-38. Bank Selection Encoding

    RXFLV. RX_FIFO Level TXFLV. TX_FIFO Level Table 5-41. Bank 3 Register Map Name MRID. Module and Revision ID SH_LCR. Shadow of LCR SH_FCR. Shadow of FIFO Control BSR. Bank Select RSVD. Reserved SuperI/O Module Bank Selected AMD Geode™ SC3200 Processor Data Book...

  • Page 131: Table 5-42. Bank 0 Bit Map

    04h-07h RSVD When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130. AMD Geode™ SC3200 Processor Data Book Table 5-42. Bank 0 Bit Map Bits...

  • Page 132: Table 5-44. Bank 2 Bit Map

    BSR[6:0] (Bank Select) RSVD PRESL[1:0] Reserved RSVD RSVD Table 5-45. Bank 3 Bit Map Bits MID[3:0] SBRK STKP TXFHT[1:0] RSVD BSR[6:0] (Bank Select) RSVD SuperI/O Module RSVD EXT_SL RSVD RFL[4:0] TFL[4:0] RID[3:0] WLS[1:0] TXSR RXSR FIFO_EN AMD Geode™ SC3200 Processor Data Book...

  • Page 133: Figure 5-19. Ircp/Sp3 Register Bank Architecture

    Banks 0 through 7. Offset Type When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-47. AMD Geode™ SC3200 Processor Data Book Bank 0 Offset 07h Offset 06h...

  • Page 134: Table 5-47. Bank Selection Encoding

    BGD(H). Baud Generator Divisor Port (High Byte) EXCR1. Extended Control 1 BSR. Bank Select EXCR2. Extended Control 2 RSVD. Reserved TXFLV. TX FIFO Level RXFLV. RX FIFO Level SuperI/O Module Bank Selected Functionality UART + IR IR Only AMD Geode™ SC3200 Processor Data Book...

  • Page 135: Table 5-50. Bank 3 Register Map

    SuperI/O Module Offset Type 04h-07h Offset Type Offset Type AMD Geode™ SC3200 Processor Data Book Table 5-50. Bank 3 Register Map Name MID. Module and Revision Identification SH_LCR. Link Control Shadow SH_FCR. FIFO Control Shadow BSR. Bank Select RSVD. Reserved Table 5-51.

  • Page 136: Table 5-53. Bank 6 Register Map

    LS_IE TXLDL_IE RXHDL_IE MS_IE LS_IE TXLDL_IE RXHDL_IE RXFT IPR[1:0] MS_EV LS_EV/ TXLDL_EV RXHDL_EV TXHLT_EV RSVD TXSR RXSR FIFO_EN WLS[1:0] ISEN/ RILP DCDLP TX_DFR DMA_EN BAD_CRC DDCD TERI DDSR TXHFE S_EOT FEND_INF RXF_TOUT AMD Geode™ SC3200 Processor Data Book RXDA DCTS...

  • Page 137: Table 5-56. Bank 1 Bit Map

    Offset Name TMR(L) TMR(H) IRCR1 BKSE TFRL(L)/ TFRCC(L) TFRL(H)/ TFRCC(H) AMD Geode™ SC3200 Processor Data Book Table 5-56. Bank 1 Bit Map Bits LBGD[7:0] (Low Byte Data) LBGD[15:8] (High Byte Data) RSVD SBRK STKP BSR[6:0] (Bank Select) RSVD Table 5-57. Bank 2 Bit Map...

  • Page 138: Table 5-60. Bank 5 Bit Map

    RXHSC RCDM_DS BSR[6:0] (Bank Select) SIRC[2:0] RSVD IRSL0_DS RXINV IRSL21_DS SuperI/O Module TX_MS MDRS IRMSSL IR_FDPLX BAD_CRC OVR1 RSVD TXCRC_INV TXCRC_DS MPW[3:0] SPW[3:0] FPL[3:0] DFR[4:0] MCFR[4:0] RSVD TXHSC RC_MMD[1:0] IRID3 IRIC[2:0] RSVD AMD Geode™ SC3200 Processor Data Book OVR2 RSVD...

  • Page 139: 6.0Core Logic Module

    • PCI 2.1 compliant • PCI master for AC97 and IDE controllers • Subtractive agent for unclaimed transactions • Supports PCI initiator-to-Sub-ISA cycle translations AMD Geode™ SC3200 Processor Data Book 32581C 6.0Core Logic Module • PCI-to-Sub-ISA interrupt mapper/translator • External PCI bus —...

  • Page 140: Module Architecture

    • ACPI compliant power management (includes GPIO interfaces, such as joystick) • Integrated audio controller • Low Pin Count (LPC) Interface Fast-PCI 33-66 MHz PCI Interface 33 MHz Config. Reg. X-Bus Legacy ISA/PIC/PIT/DMA Sub-ISA Core Logic Module AC97 Audio Controller AMD Geode™ SC3200 Processor Data Book...
  • Page 141 The Core Logic module decodes the serial packet after each transmission and performs the power management tasks related to video retrace. For more information on the Serial Packet register refer to the AMD Geode™ GX1 Processor Data Book.

  • Page 142: Ide Controller

    PIO mode which that device reports it supports. The PIO command cycle timing for a particular device must be the timing value for the lowest PIO mode for both devices on the channel. AMD Geode™ SC3200 Processor Data Book Core Logic Module...

  • Page 143: Table 6-1. Physical Region Descriptor Format

    31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Memory Region Physical Base Address [31:1] (IDE Data Buffer) Reserved AMD Geode™ SC3200 Processor Data Book Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor (PRD) as illus- trated in Table 6-1.

  • Page 144: Table 6-2. Ultradma/33 Signal Definitions

    Also listed in the bit formats are recommended values for both Multiword DMA Modes 0-2 and UltraDMA/33 Modes 0-2. Note that these are only recommended settings and are not 100% tested. Core Logic Module AMD Geode™ SC3200 Processor Data Book...

  • Page 145: Universal Serial Bus

    — DOCR# is asserted on memory read transactions from DOCCS# window (i.e., when both DOCCS# and MEMR# are active, DOCR# is active; otherwise, it is inactive). AMD Geode™ SC3200 Processor Data Book 32581C • DOCW — DOCW# is asserted on memory write transactions to DOCCS# window (i.e., when both DOCCS# and...

  • Page 146: Figure 6-2. Non-Posted Fast-Pci To Isa Access

    PCI cycles from occupying too much band- width and allows access to other PCI traffic. Figure 6-3 on page 147 shows the relationship of PCI cycles to an ISA cycle with PCI delayed transactions enabled. AMD Geode™ SC3200 Processor Data Book Core Logic Module...

  • Page 147: Figure 6-3. Pci To Isa Cycles With Delayed Transaction Enabled

    PCI data bus. When the DMA requestor is the bus owner, the Core Logic module allows 8/16-bit data transfer between the Sub-ISA bus and the PCI data bus. AMD Geode™ SC3200 Processor Data Book 32581C 6.2.5.4 I/O Recovery Delays...

  • Page 148: Figure 6-4. Isa Dma Read From Pci Memory

    PCI cycle, asserts FRAME#, and negates an internal IOCHRDY. This assures the DMA cycle does not complete before the PCI cycle has provided or accepted the data. IOCHRDY is internally asserted when IRDY# and TRDY# are sampled active. AMD Geode™ SC3200 Processor Data Book Core Logic Module...

  • Page 149: Table 6-3. Cycle Multiplexed Pci / Sub-Isa Balls

    74HCT245 or 74FCT245 type transceivers. The RD# (an AND of IOR#, MEMR#) signal can be used as DIR control while TRDE# is used as enable control. AMD Geode™ SC3200 Processor Data Book Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls AD10...

  • Page 150: Figure 6-6. Pci Change To Sub-Isa And Back

    Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 transfer 16-bit WORDs on even byte boundaries only. Channels 5 through 7 are not supported. AMD Geode™ SC3200 Processor Data Book Core Logic Module...
  • Page 151 For read transfer types, the Core Logic module reads data from memory and write it to the I/O device associated with the DMA channel. AMD Geode™ SC3200 Processor Data Book 32581C For write transfer types, the Core Logic module reads data from the I/O device associated with the DMA channel and write to the memory.

  • Page 152: Figure 6-7. Pit Timer

    PIT state by reading the PIT’s counter and write only registers. The read sequence for the shadow register is listed in F0 Index BAh (see Table 6-29 on page 188). AMD Geode™ SC3200 Processor Data Book Core Logic Module IRQ0 F0 Index 50h[4]...

  • Page 153: Figure 6-8. Pic Interrupt Controllers

    IRQ14 (muxed with TFTD1), and IRQ9 (muxed with IDE_DATA6) More of the IRQs are available through the use of SERIRQ (muxed with GPIO39) function. See Table 6-4. AMD Geode™ SC3200 Processor Data Book Table 6-4. PIC Interrupt Mapping Master IRQ0...

  • Page 154: Figure 6-9. Pci And Irq Interrupt Mapping

    A20M# state and the SMI handler sets the A20M# state inside the GX1 module. This method is used for both the Port 092h (PS/2) and Port 061h (key- board) methods of controlling A20M#. AMD Geode™ SC3200 Processor Data Book Core Logic Module Level/Edge Sensitivity...

  • Page 155: Keyboard Support

    Bit 2 = ERR_EN (PERR#/SERR# Enable) Bit 3 = IOCHK_EN (IOCHK Enable) I/O Port 070h: RTC Index Register (WO) Bit 72 = NMI (NMI Enable) AMD Geode™ SC3200 Processor Data Book 6.2.8 Keyboard Support The Core Logic module can actively decode the keyboard controller I/O Ports 060h, 062h, 064h and 066h, and gener- ate an LPC bus cycle.

  • Page 156: Power Management Logic

    In this state, the GX1 module is in Suspend Refresh mode (for details, see the Power Management section of the AMD Geode™ GX1 Processor Data Book, and Section 6.2.9.5 "Usage Hints" on page 159). PCI arbitration should be disabled prior entering the C3...

  • Page 157: Table 6-5. Wakeup Events Capability

    IRRX1 (Infrared) GPWIO[2:0] RI2# (UART2) Temporarily exits state. AMD Geode™ SC3200 Processor Data Book decide which other system devices to power off with the PWRCNT1 pin. No reset is performed, when exiting this state. The SC3200 keeps all context in this state. This state corresponds to ACPI sleep state S1, with lower power and longer wake time than in SL1.

  • Page 158: Table 6-6. Power Planes Control Signals Vs. Sleep States

    Event Power Button Power Button Override Bus Master Request Thermal Monitoring On or Off On or Off ACPI Timer GPIO SDATA_IN2 (AC97) IRRX1 On or Off RI2# GPWIO Internal SMI signal Core Logic Module AMD Geode™ SC3200 Processor Data Book...
  • Page 159 • When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are de-asserted immediately regardless of the PWRBTN_EN bit. AMD Geode™ SC3200 Processor Data Book 32581C Power Button Override When PWRBTN# is 0 for more than four seconds, ONCTL# and PWRCNT[2:1] are de-asserted (i.e., the system transi- tions to the SL5 state, “Soft Off”).
  • Page 160 Video activity is defined as any access to the VGA register space, the VGA frame buffer, the graphics accelerator control registers and the configured graphics frame buffer. AMD Geode™ SC3200 Processor Data Book Core Logic Module 6.2.10.3 "Peripheral...
  • Page 161 If F0 Index 96h[1] = 1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable register (F1BAR0+I/O Offset 08h). AMD Geode™ SC3200 Processor Data Book 32581C The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM.
  • Page 162 F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI is generated when bit 23 toggles. AMD Geode™ SC3200 Processor Data Book Core Logic Module...

  • Page 163: Figure 6-11. General Purpose Timer And Udef Trap Smi Tree Example

    Other_SMI Top Level Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example AMD Geode™ SC3200 Processor Data Book These two registers are identical except that reading the register at F1BAR0+I/O Offset 02h clears the status. Since all SMI sources report to the Top Level SMI Status register, many of its bits combine a large number of events requiring a second level of SMI status reporting.

  • Page 164: Table 6-9. Device Power Management Programming Summary

    F1BAR0+I/O Offset 04h[4] 88h[7:0], 89h[7:0], 8Bh[4] F1BAR0+I/O Offset 04h[0] 8Ah[7:0], 8Bh[5,3,2] F1BAR0+I/O Offset 04h[1] 94h[15:0], 96h[2:0] 8Dh[7:0], A8h[15:0] 8Ch[7:0] AMD Geode™ SC3200 Processor Data Book Core Logic Module Second Level SMI Status/With Clear F5h[3] F5h[2] F5h[1] F5h[7] F1BAR0+I/O Offset 02h[6]...

  • Page 165: Gpio Interface

    16-Bit output to codec. Slot in use is determined by F3BAR0+Memory Offset 08h[19]. 6 or 11 16-Bit input from codec. Slot in use is determined by F3BAR0+Memory Offset 08h[20]. AMD Geode™ SC3200 Processor Data Book 32581C • Trap accesses for MIDI UART interface at I/O Port 300h- 301h or 330h-331h.

  • Page 166: Table 6-11. Physical Region Descriptor Format

    SMI generated by the EOP from the first PRD allows the software to refill Audio Buffer_1. The second SMI refills Audio Buffer_2. The third SMI refills Audio Buffer_1 and so on. Byte 2 Reserved Core Logic Module Byte 1 Byte 0 Size [15:1] AMD Geode™ SC3200 Processor Data Book...

  • Page 167: Figure 6-12. Prd Table Example

    EOT = 0 EOP = 0 JMP = 1 AMD Geode™ SC3200 Processor Data Book Table Address register is incremented by 08h and is now pointing to PRD_3. The SMI Status register is read to clear the End of Page status flag. Since Audio Buffer_1 is now empty, the software can refill it.

  • Page 168: Figure 6-13. Ac97 V2.0 Codec Signal Connections

    The bit formats for these registers are given in Table 6-38 "F3BAR0+Memory Offset: Audio Configuration Registers" on page 262. BIT_CLK XTAL_I SYNC Codec1 PC_BEEP SDATA_OUT SDATA_IN BIT_CLK XTAL_I Codec2 SYNC (Optional) PC_BEEP SDATA_OUT SDATA_IN2 AMD Geode™ SC3200 Processor Data Book Core Logic Module...
  • Page 169 • I/O Trap SMI and Fast Write Status Register (F3BAR0+Memory Offset 14h) • I/O Trap SMI Enable Register (F3BAR0+Memory Offset 18h) AMD Geode™ SC3200 Processor Data Book 32581C Audio SMI Status Reporting Registers: The Top SMI Status Mirror and Status registers are the top...

  • Page 170: Figure 6-14. Audio Smi Tree Example

    Offset 14h Read to Clear to determine third-level source of SMI Bits [31:14] Other_RO Bit 13 SMI_SC/FM_TRAP Bit 12 Take SMI_DMA_TRAP Appropriate Bit 11 Action SMI_MPU_TRAP Bit 10 SMI_SC/FM_TRAP Bits [9:0] Other_RO Third Level AMD Geode™ SC3200 Processor Data Book...

  • Page 171: Figure 6-15. Typical Setup

    The mother- board BIOS should be able to configure all devices at boot. AMD Geode™ SC3200 Processor Data Book 32581C • Support desktop and mobile implementations. • Enable support of a variable number of wait states.

  • Page 172: Table 6-12. Cycle Types

    • Only 8- or 16-bit DMA, depending on channel number. Does not support the optional larger transfer sizes. • Only one external DRQ pin. AMD Geode™ SC3200 Processor Data Book Core Logic Module (Bytes) 1 or 2 1 or 2...

  • Page 173: Register Descriptions

    The device number depends upon the IDSEL Strap Override bit (F5BAR0+I/O Offset 04h[0]). This bit allows selection of the address lines to be used as the IDSEL. By Default: IDSEL = AD28 (1001 0) for F0-F5, AD29 (1001 1) for PCIUSB. AMD Geode™ SC3200 Processor Data Book 6.3.1...

  • Page 174: Table 6-14. F0: Pci Header/Bridge Configuration Registers For Gpio And Lpc Support Summary

    Page 193 Page 193 Page 193 FFFFFFFFh Page 194 Page 194 Page 194 Page 195 Page 195 Page 196 Page 196 Page 196 Page 197 Page 197 Page 197 00000000h Page 198 Page 198 AMD Geode™ SC3200 Processor Data Book...
  • Page 175 Suspend Notebook Command Register B0h-B3h Reserved Floppy Port 3F2h Shadow Register Floppy Port 3F7h Shadow Register Floppy Port 1F2h Shadow Register Floppy Port 1F7h Shadow Register AMD Geode™ SC3200 Processor Data Book 32581C Reset Reference Value (Table 6-29) 0000FFF0h Page 198...
  • Page 176 Page 216 00000000h Page 216 00000000h Page 216 Page 217 Page 217 Page 217 Page 217 Page 217 Page 217 Page 218 Page 218 Page 218 Page 218 Page 219 Page 220 Page 221 AMD Geode™ SC3200 Processor Data Book...

  • Page 177: Table 6-15. F0Bar0: Gpio Support Registers Summary

    LAD_D0 — LPC Address Decode 0 Register 18h-1Bh LAD_D1 — LPC Address Decode 1 Register 1Ch-1Fh LPC_ERR_SMI — LPC Error SMI Register 20h-23h LPC_ERR_ADD — LPC Error Address Register AMD Geode™ SC3200 Processor Data Book 32581C Reset Reference Value (Table 6-30) FFFFFFFFh...

  • Page 178: Table 6-17. F1: Pci Header Registers For Smi Status And Acpi Support Summary

    Value (Table 6-33) 0000h Page 235 0000h Page 236 0000h Page 238 0000h Page 239 0000h Page 240 Page 240 xxxxxxxxh Page 240 0000h Page 240 0000h Page 241 00000000h Page 241 Page 244 AMD Geode™ SC3200 Processor Data Book...

  • Page 179: Table 6-19. F1Bar1: Acpi Support Registers Summary

    GPWIO Data Register Reserved 18h-1Bh ACPI SCI_ROUTING Register 1Ch-1Fh PM_TMR — PM Timer Register PM2_CNT — PM2 Control Register 21h-FFh Not Used AMD Geode™ SC3200 Processor Data Book 32581C Reset Reference Value (Table 6-34) 00000000h Page 245 Page 245 Page 245...

  • Page 180: Table 6-20. F2: Pci Header Registers For Ide Controller Support Summary

    100Bh Page 255 0502h Page 255 Page 256 00009172h Page 256 00077771h Page 257 00009172h Page 257 00077771h Page 257 00009172h Page 258 00077771h Page 258 00009172h Page 258 00077771h Page 258 Page 258 AMD Geode™ SC3200 Processor Data Book...

  • Page 181: Table 6-21. F2Bar4: Ide Controller Support Registers Summary

    VSA audio interface control register block (summarized in Table 6-23). 14h-2Bh Reserved 2Ch-2Dh Subsystem Vendor ID 2Eh-2Fh Subsystem ID 30h-FFh Reserved AMD Geode™ SC3200 Processor Data Book 32581C Name 00000000h 00000000h 040100h 00000000h Reset Reference Value (Table 6-36)

  • Page 182: Table 6-23. F3Bar0: Audio Support Registers Summary

    Page 272 Page 272 00000000h Page 272 Page 273 Page 273 Page 273 00000000h Page 273 Page 274 Page 274 Page 274 00000000h Page 274 Page 275 Page 275 Page 275 00000000h Page 275 AMD Geode™ SC3200 Processor Data Book...

  • Page 183: Table 6-24. F5: Pci Header Registers For X-Bus Expansion Support Summary

    Width I/O Offset (Bits) Type Name 00h-03h I/O Control Register 1 04h-07h I/O Control Register 2 08h-0Bh I/O Control Register 3 AMD Geode™ SC3200 Processor Data Book 32581C Reset Reference Value (Table 6-39) 100Bh Page 276 0505h Page 276 0000h...

  • Page 184: Table 6-26. Pciusb: Usb Pci Configuration Register Summary

    Page 283 Page 283 Page 283 00000000h Page 283 Page 284 0E11h Page 284 A0F8h Page 284 Page 284 Page 284 Page 284 Page 284 Page 284 000F0000h Page 284 Page 284 Page 284 AMD Geode™ SC3200 Processor Data Book...

  • Page 185: Table 6-27. Usb_Bar: Usb Controller Registers Summary

    58h-5Bh HcRhPortStatus[2] 5Ch-5Fh HcRhPortStatus[3] 60h-9Fh Reserved 100h-103h HceControl 104h-107h HceInput 108h-10Dh HceOutput 10Ch-10Fh HceStatus AMD Geode™ SC3200 Processor Data Book 32581C Reference Reset Value (Table 6-42) 00000110h Page 285 00000000h Page 285 00000000h Page 285 00000000h Page 285 00000000h Page 286...

  • Page 186: Table 6-28. Isa Legacy I/O Register Summary

    Page 299 Page 299 Page 299 Page 299 Page 299 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 Page 300 AMD Geode™ SC3200 Processor Data Book...
  • Page 187 Secondary IDE Registers 376h-377h 1F0-1F7h/ Primary IDE Registers 3F6h-3F7h 4D0h Interrupt Edge/Level Select Register 1 4D1h Interrupt Edge/Level Select Register 2 AMD Geode™ SC3200 Processor Data Book 32581C Reference Page 300 Page 300 Page 300 Page 300 Page 301 Page 301...

  • Page 188: Chipset Register Space

    (described in Section 6.4.1.1 "GPIO Support Registers" on page 222 and Section 6.4.1.2 "LPC Support Registers" on page 226). Vendor Identification Register (RO) Device Identification Register (RO) PCI Command Register (R/W) Reset Value: 100Bh Reset Value: 0500h Reset Value: 000Fh AMD Geode™ SC3200 Processor Data Book...
  • Page 189 Fast Back-to-Back Capable. (Read Only) Enables the Core Logic module, as a target, to accept fast back-to-back trans- actions. 0: Disable. 1: Enable. This bit is always set to 1. Reserved. (Read Only) Must be set to 0 for future use. AMD Geode™ SC3200 Processor Data Book PCI Status Register (R/W) 32581C Reset Value: 0280h...
  • Page 190 Reset Value: 00h Reset Value: 060100h Reset Value: 00h Reset Value: 00h Reset Value: 80h Reset Value: 00h Reset Value: 00000001h Reset Value: 00000001h Reset Value: 00h Reset Value: 100Bh Reset Value: 0500h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 191 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9]. Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5]. AMD Geode™ SC3200 Processor Data Book PCI Function Control Register 1 (R/W) PCI Function Control Register 2 (R/W)
  • Page 192 Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved Delayed Transactions Register (R/W) Reset Control Register (R/W) Reset Value: 00h Reset Value: 02h Reset Value: 01h AMD Geode™ SC3200 Processor Data Book...
  • Page 193 F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers. 0: Disable. 1: Enable. Reserved. Must be set to 0. Index 48h-4Bh AMD Geode™ SC3200 Processor Data Book Reserved PCI Functions Enable Register (R/W) Miscellaneous Enable Register (R/W) Reserved...
  • Page 194 PIT Control/ISA CLK Divider (R/W) 100: Divide by 5 101: Divide by 6 110: Divide by 7 111: Divide by 8 ISA I/O Recovery Control Register (R/W) Reset Value: FFFFFFFFh Reset Value: 7Bh Reset Value: 40h AMD Geode™ SC3200 Processor Data Book...
  • Page 195 Generate SMI on A20M# Toggle. 0: Disable. 1: Enable. This bit must be set to 1. SMI status is reported at F1BAR0+I/O Offset 00h/02h[7]. AMD Geode™ SC3200 Processor Data Book ROM/AT Logic Control Register (R/W) Alternate CPU Support Register (R/W) 32581C Reset Value: 98h...
  • Page 196 ROM configuration is at F0 Index 52h[2:0]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Reserved Decode Control Register 1 (R/W) Decode Control Register 2 (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 00h Reset Value: 01h Reset Value: 20h...
  • Page 197 0011: IRQ3 INTC# (Ball C9) Target Interrupt. 0000: Disable 0001: IRQ1 0010: Reserved 0011: IRQ3 Index 5Eh-5Fh AMD Geode™ SC3200 Processor Data Book PCI Interrupt Steering Register 1 (R/W) 0100: IRQ4 1000: Reserved 0101: IRQ5 1001: IRQ9 0110: IRQ6 1010: IRQ10...
  • Page 198 Reserved. Must be set to 0. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 ACPI Control Register (R/W) Reserved ROM Mask Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 00000000h Reset Value: 00h Reset Value: 0000FFF0h...
  • Page 199 00000: 1 Byte 00001: 2 Bytes 00011: 4 Bytes 00111: 8 Bytes Index 77h AMD Geode™ SC3200 Processor Data Book IOCS1# Base Address Register (R/W) IOCS1# Control Register (R/W) 01111: 16 Bytes 11111: 32 Bytes All other combinations are reserved.
  • Page 200 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 DOCCS# Base Address Register (R/W) DOCCS# Control Register (R/W) Power Management Enable Register 1 (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 201 UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register). Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[4]. AMD Geode™ SC3200 Processor Data Book Power Management Enable Register 2 (R/W) 32581C...
  • Page 202 If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book...
  • Page 203 — COM4: I/O Port 2E8h-2EFh. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[2]. AMD Geode™ SC3200 Processor Data Book Power Management Enable Register 3 (R/W) 32581C Reset Value: 00h...
  • Page 204 VGA Timer. SMI status is reported at F1BAR0+I/O Offset 00h/02h[6] (top level only). Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Power Management Enable Register 4 (R/W) Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 205 GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin. 0: No. 1: Yes. To enable SMI generation: 1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0. 2) Set F1BAR1+I/O Offset 15h[4] to 1. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00h...
  • Page 206 Idle Timer Count Register (F0 Index 98h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 81h[0] to 1. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book Reset Value: 00h...
  • Page 207 Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the primary hard disk. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[0] to 1. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00h...
  • Page 208 162 for a discussion on the limitations of producing count error with small values. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book Reset Value: 00h Reset Value: 00h...
  • Page 209 Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity. 0: Disable. 1: Enable. Any access to the primary hard disk address range selected in F0 Index 93h[5], reloads General Purpose Timer 1. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00h...
  • Page 210 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 IRQ Speedup Timer Count Register (R/W) Video Speedup Timer Count Register (R/W) Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 211 The ratio of SUSP# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the power manager to reduce GX1 module power consumption. This counter is prematurely reset if an enabled speedup event occurs (i.e., IRQ and video speedups). AMD Geode™ SC3200 Processor Data Book VGA Timer Count Register (R/W) Reserved...
  • Page 212 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Suspend Configuration Register (R/W) Reserved Floppy Disk Idle Timer Count Register (R/W) Reset Value: 00h Reset Value: 00h Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h AMD Geode™ SC3200 Processor Data Book...
  • Page 213 Software clears the overflow register when new evaluations are to begin. The count contained in this register can be combined with other data to determine the type of video accesses present in the system. Index AAh-ABh AMD Geode™ SC3200 Processor Data Book Video Idle Timer Count Register (R/W) Video Overflow Count Register (R/W)
  • Page 214 Floppy Port 372h Shadow Register (RO) Floppy Port 377h Shadow Register (RO) Reset Value: 0000h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: xxh Reset Value: xxh Reset Value: xxh Reset Value: xxh AMD Geode™ SC3200 Processor Data Book...
  • Page 215 Note: The LSB/MSB of the count is the Counter base value, not the current value. Bits [7:6] of the command words are not used. AMD Geode™ SC3200 Processor Data Book DMA Shadow Register (RO) PIC Shadow Register (RO) PIT Shadow Register (RO)
  • Page 216 1011: 11 ms Reserved Reset Value: xxh Reset Value: 00h 1100: 12 ms 1101: 13 ms 1110: 14 ms 1111: 15 ms Reset Value: 00h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 217 Software SMI. A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions. Index D1h-EBh AMD Geode™ SC3200 Processor Data Book User Defined Device 1 Control Register (R/W) User Defined Device 2 Control Register (R/W)
  • Page 218 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Timer Test Register (R/W) Reserved Second Level PME/SMI Status Register 1 (RC) Second Level PME/SMI Status Register 2 (RC) Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 219 Hard Disk Idle Timer Count register (F0 Index ACh). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[7] = 1. AMD Geode™ SC3200 Processor Data Book Second Level PME/SMI Status Register 3 (RC) 32581C Reset Value: 00h...
  • Page 220 — IRRX1 (CEIR) To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Second Level PME/SMI Status Register 4 (RC) Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 221 ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch) MSB toggle. 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[5] = 1. Index F8h-FFh AMD Geode™ SC3200 Processor Data Book 32581C Reserved Reset Value: 00h...

  • Page 222: Table 6-30. F0Bar0+I/O Offset: Gpio Configuration Registers

    GPDO0 — GPIO Data Out 0 Register (R/W) GPDI0 — GPIO Data In 0 Register (RO) GPST0 — GPIO Status 0 Register (R/W1C) Reset Value: FFFFFFFFh Reset Value: FFFFFFFFh Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 223 GPIO Signal Configuration Select Register (R/W) 31:6 Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book GPDO1 — GPIO Data Out 1 Register (R/W) GPDI1 — GPIO Data In 1 Register (RO) GPST1 — GPIO Status 1 Register (R/W1C)
  • Page 224 110110 = GPIO54 110111 = GPIO55 111000 = GPIO56 111001 = GPIO57 111010 = GPIO58 111011 = GPIO59 111100 = GPIO60 111101 = GPIO61 111110 = GPIO62 111111 = GPIO63 (Note) AMD Geode™ SC3200 Processor Data Book Reset Value: 00000044h...
  • Page 225 1: Enable. Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this bit to be 0). AMD Geode™ SC3200 Processor Data Book GPIO Reset Control Register (R/W) 32581C Reset Value: 00000000h...

  • Page 226: Table 6-31. F0Bar1+I/O Offset: Lpc Interface Configuration Registers

    LPC bus specification 1.0, with the following exceptions: • Only 8- or 16-bit DMA, depending on channel number. Does not support the optional larger transfer sizes. • Only one external DRQ pin. AMD Geode™ SC3200 Processor Data Book Reset Value: 00000000h...
  • Page 227 Reserved. Must be set to 0. IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00000000h...
  • Page 228 IRQ3 Polarity. If LPC is selected as the interface source for IRQ3 (F0BAR1+I/O Offset 00h[3] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book...
  • Page 229 1: Disable. DRQ3 Source. Selects the interface source of the DRQ3 signal. 0: ISA - DRQ3 (unavailable externally). 1: LPC - LDRQ# (ball L28). AMD Geode™ SC3200 Processor Data Book 0100: 21 frames 1000: 25 frames 0101: 22 frames 1001: 26 frames...
  • Page 230 LPC Serial Port 1 Addressing. Serial Port 1 addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[7:5]. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book Reset Value: 00000000h...
  • Page 231 10: 3BCh-3BFh (+7BCh-7BFh for ECP) Selected address range is enabled via F0BAR1+I/O Offset 10h[0]. Note: 279h is read only, writes are forwarded to ISA for PnP. AMD Geode™ SC3200 Processor Data Book 0100: 204h 1000: 208h 0101: 205h 1001: 209h...
  • Page 232 LPC Multiple Errors Status. Indicates whether or not multiple errors have occurred on LPC. 0: No. 1: Yes. Write 1 to clear. Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 AMD Geode™ SC3200 Processor Data Book Reset Value: 00000000h Reset Value: 00000080h...
  • Page 233 LPC Error Memory Status. Indicates whether or not an error was generated during a memory operation on LPC. 0: No. 1: Yes. Write 1 to clear. Offset 20h-23h LPC_ERR_ADD — LPC Error Address Register (RO) 31:0 LPC Error Address. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00000000h...

  • Page 234: Table 6-32. F1: Pci Header Registers For Smi Status And Acpi Support

    Reset Value: 068000h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000001h Reset Value: 00h Reset Value: 100Bh Reset Value: 0501h Reset Value: 00h Reset Value: 00000001h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 235: Table 6-33. F1Bar0+I/O Offset: Smi Status Registers

    This method of controlling the internal A20M# in the GX1 module is used instead of a pin. To enable SMI generation, set F0 Index 53h[0] to 1. AMD Geode™ SC3200 Processor Data Book 32581C The registers at F1BAR0+I/O Offset 50h-FFh can also be accessed F0 Index 50h-FFh.
  • Page 236 SMI Source is Warm Reset Command. (Read to Clear) Indicates whether or not an SMI was caused by Warm Reset command 0: No. 1: Yes. Core Logic Module - SMI Status and ACPI Registers - Function 1 Top Level PME/SMI Status Register (RO/RC) Reset Value: 0000h AMD Geode™ SC3200 Processor Data Book...
  • Page 237 SMI Source is ACPI. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by an access (read or write) to one of the ACPI registers (F1BAR1). 0: No. 1: Yes. The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h. AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 238 To enable SMI generation, set F0 Index 83h[1] = 1. Core Logic Module - SMI Status and ACPI Registers - Function 1 Second Level General Traps & Timers PME/SMI Status Mirror Register (RO) Reset Value: 0000h AMD Geode™ SC3200 Processor Data Book...
  • Page 239 SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of Gen- eral Purpose Timer 1 (F0 Index 88h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[0] = 1. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 0000h...
  • Page 240 Core Logic Module - SMI Status and ACPI Registers - Function 1 Reserved ACPI Timer Register (RO) Second Level ACPI PME/SMI Status Mirror Register (RO) AMD Geode™ SC3200 Processor Data Book Reset Value: 0000h Reset Value: 00h Reset Value: xxxxxxxxh Reset Value: 0000h...
  • Page 241 EXT_SMI6 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6 0: No. 1: Yes. To enable SMI generation, set bit 6 to 1. AMD Geode™ SC3200 Processor Data Book External SMI Register (R/W) 32581C Reset Value: 0000h...
  • Page 242 EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3. 0: No. 1: Yes. To enable SMI generation, set bit 3 to 1. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 243 EXT_SMI1 SMI Enable. When this bit is asserted, allow EXT_SMI1 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 17 (RC) and 9 (RO). AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 244 50h-FFh figuration Registers for GPIO and LPC Support" on page 188 for more information about these registers. Core Logic Module - SMI Status and ACPI Registers - Function 1 Not Used AMD Geode™ SC3200 Processor Data Book Reset Value: 00h...

  • Page 245: Table 6-34. F1Bar1+I/O Offset: Acpi Support Registers

    1: Disable. (No debounce) GPWIO2 pin does not have debounce capability. Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book are located. Table 6-34 shows the I/O mapped ACPI Sup- port registers accessed through F1BAR1. P_CNT — Processor Control Register (R/W)
  • Page 246 For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[5] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in the general description of this register.) Write 1 to clear. Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC3200 Processor Data Book Reset Value: 0000h...
  • Page 247 ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch). Disable. Enable Offset 0Ch-0Dh 15:14 Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book PM1A_CNT — PM1A Control Register (R/W) 32581C Reset Value: 0000h Reset Value: 0000h...
  • Page 248 Write 1 to clear. Core Logic Module - SMI Status and ACPI Registers - Function 1 100: Sleep State SL4 101: Sleep State SL5 (Soft off) 110: Reserved 111: Reserved ACPI_BIOS_STS Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 00h...
  • Page 249 Set F1BAR1+I/O Offset 12h[8] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above). If F1BAR1+I/O Offset 15h[4] = 1 it overrides these settings and GPWIO0 generates an SMI and the status is reported in F1BAR0+00h/02h[0]. AMD Geode™ SC3200 Processor Data Book ACPI_BIOS_EN Register (R/W) 32581C Reset Value: 00h...
  • Page 250 For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.) Core Logic Module - SMI Status and ACPI Registers - Function 1 AMD Geode™ SC3200 Processor Data Book...
  • Page 251 PWR_U_REQ_EN. Allow power-up request events from the SuperI/O module to generate an SCI. 0: Disable. 1: Enable. A power-up request event is defined as any of the following events/activities: Modem, Telephone, Keyboard, Mouse, CEIR (Consumer Electronic Infrared) AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 0000h...
  • Page 252 GPWIO0_DIR. Selects the direction of the GPWIO0. 0: Input. 1: Output. Core Logic Module - SMI Status and ACPI Registers - Function 1 GPWIO Control Register 1 (R/W) GPWIO Control Register 2 (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 00h Reset Value: 00h...
  • Page 253 Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2]. Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[1]. Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book GPWIO Data Register (R/W) Reserved ACPI SCI_ROUTING Register (R/W)
  • Page 254 1010: IRQ10 0011: IRQ7 1011: IRQ11 ACPI Timer Register (RO) PM2_CNT — PM2 Control Register (R/W) Reserved 1100: IRQ12 1101: IRQ13 1110: IRQ14 1111: IRQ15 Reset Value: xxxxxxxxh Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 255: Table 6-35. F2: Pci Header/Channels 0 And 1 Registers For Ide Controller Configuration

    Index 24h-2Bh Index 2Ch-2Dh Index 2Eh-2Fh AMD Geode™ SC3200 Processor Data Book Located in the PCI Header Registers of F2 is a Base Address Register (F2BAR4) used for pointing to the regis- ter space designated for support of the IDE controllers, described later in this section.
  • Page 256 Data cycle address Setup Time (value + 1 cycle). Core Logic Module - IDE Controller Registers - Function 2 Reserved Channel 0 Drive 0 PIO Register (R/W) Reset Value: 00h Reset Value: 00009172h AMD Geode™ SC3200 Processor Data Book...
  • Page 257 Note: The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved. AMD Geode™ SC3200 Processor Data Book Channel 0 Drive 0 DMA Control Register (R/W) Channel 0 Drive 1 PIO Register (R/W)
  • Page 258 Channel 1 Drive 0 DMA Control Register (R/W) Channel 1 Drive 1 PIO Register (R/W) Channel 1 Drive 1 DMA Control Register (R/W) Reserved Reset Value: 00009172h Reset Value: 00077771h Reset Value: 00009172h Reset Value: 00077771h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 259: Table 6-36. F2Bar4+I/O Offset: Ide Controller Configuration Registers

    = 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD. When read, this register points to the next PRD. Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book 32581C mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4.
  • Page 260 When read, this register points to the next PRD. Reserved. Must be set to 0. Core Logic Module - IDE Controller Registers - Function 2 Not Used Not Used AMD Geode™ SC3200 Processor Data Book Reset Value: 00h Reset Value: 00h Reset Value: 00000000h...

  • Page 261: Table 6-37. F3: Pci Header Registers For Audio Configuration

    Index 2Ch-2Dh Index 2Eh-2Fh Index 30h-FFh AMD Geode™ SC3200 Processor Data Book A Base Address register (F3BAR0), located in the PCI Header registers of F3, is used for pointing to the register space designated for support of audio, described later in this section.

  • Page 262: Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers

    Core Logic Module - Audio Registers - Function 3 memory mapped audio configuration registers that are accessed through F3BAR0. Codec GPIO Status Register (R/W) Codec GPIO Control Register (R/W) Codec Status Register (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 263 An SMI is then generated when the End of Page bit is set in the Audio Bus Master 3 SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). AMD Geode™ SC3200 Processor Data Book Codec Command Register (R/W) Second Level Audio SMI Status Register (RC)
  • Page 264 End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). The End of Page bit must be cleared before this bit can be cleared. Core Logic Module - Audio Registers - Function 3 Reset Value: 0000h AMD Geode™ SC3200 Processor Data Book...
  • Page 265 This is the third level of SMI status reporting. Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Top level is reported at F1BAR0+I/O Offset 00h/02h[1]. SMI generation enabling is at F3BAR0+Memory Offset 18h[2]. AMD Geode™ SC3200 Processor Data Book 32581C Reset Value: 00000000h...
  • Page 266 Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR0+Memory Offset 14h[11]. Core Logic Module - Audio Registers - Function 3 I/O Trap SMI Enable Register (R/W AMD Geode™ SC3200 Processor Data Book )Reset Value: 0000h...
  • Page 267 IRQ9 Internal. Configures IRQ9 for internal (software) or external (hardware) use. 0: External. 1: Internal. Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book 10: I/O Port 260h-26Fh 11: I/O Port 280h-28Fh Internal IRQ Enable Register (R/W)
  • Page 268 Reserved. (Write Only) Must be set to 0. Mask Internal IRQ5. (Write Only) 0: Disable. 1: Enable. Core Logic Module - Audio Registers - Function 3 Internal IRQ Control Register (R/W) Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 269 Reserved. Set to 0. Assert Masked Internal IRQ5. 0: Disable. 1: Enable. Assert Masked Internal IRQ4. 0: Disable. 1: Enable. Assert Masked Internal IRQ3. 0: Disable. 1: Enable. Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 270 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 271 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC3200 Processor Data Book Audio Bus Master 1 Command Register (R/W) Audio Bus Master 1 SMI Status Register (RC) Not Used...
  • Page 272 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 273 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC3200 Processor Data Book Audio Bus Master 3 Command Register (R/W) Audio Bus Master 3 SMI Status Register (RC) Not Used...
  • Page 274 = Loop Flag (JMP) [28:16] = Reserved (0) [15:0] = Byte Count of the Region (Size) Core Logic Module - Audio Registers - Function 3 Reset Value: 00h Reset Value: 00h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 275 The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from which data is to be transferred. Each entry consists of two DWORDs. DWORD 0: DWORD 1: AMD Geode™ SC3200 Processor Data Book Audio Bus Master 5 Command Register (R/W) Audio Bus Master 5 SMI Status Register (RC) Not Used...

  • Page 276: Table 6-39. F5: Pci Header Registers For X-Bus Expansion

    Reset Value: 0505h Reset Value: 0000h Reset Value: 0280h Reset Value: 00h Reset Value: 068000h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 277 Reserved. Must be set to 0. This bit must be set to 1, to indicate an I/O base address register. AMD Geode™ SC3200 Processor Data Book Base Address Register 3 - F5BAR3 (R/W) Base Address Register 4 - F5BAR4 (R/W)
  • Page 278 F5BAR5 Mask Address Register (R/W) F5BARx Initialized Register (R/W) Reserved Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h Reset Value: xxh Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 279 Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued) Description Index 64h-67h Scratchpad: Usually used for Configuration Block Address (R/W) BIOS writes a value, of the Configuration Block Address. Index 68h-FFh AMD Geode™ SC3200 Processor Data Book 32581C Reserved Reset Value: 00000000h...

  • Page 280: Table 6-40. F5Bar0+I/O Offset: X-Bus Expansion Registers

    1: Enable. 17:0 Reserved. Core Logic Module - X-Bus Expansion Interface - Function 5 trol support registers. Table 6-40 shows the support regis- ters accessed through F5BAR0. I/O Control Register 1 (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 010C0007h...
  • Page 281 0: Disable 1: Enable IO_TEST_PORT_REG (Debug Port Pointer). These bits are used to point to the 16-bit slice of the test port bus. AMD Geode™ SC3200 Processor Data Book I/O Control Register 2 (R/W) I/O Control Register 3 (R/W) 32581C...

  • Page 282: Bit Description

    (OHCI) specification. Registers marked as “Reserved”, and reserved bits within a register, should not be changed by software. Vendor Identification Register (RO) Device Identification Register (RO) Command Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 0E11h Reset Value: A0F8h Reset Value: 00h...
  • Page 283 Always 0. Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space. Always 0. Indicates that the operational registers are mapped into memory space. AMD Geode™ SC3200 Processor Data Book Status Register (R/W)
  • Page 284 Reserved Reset Value: 00h Reset Value: 0E11h Reset Value: A0F8h Reset Value: 00h Reset Value: 00h Reset Value: 01h Reset Value: 00h Reset Value: 50h Reset Value: 000F0000h Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 285: Table 6-42. Usb_Bar+Memory Offset: Usb Controller Registers

    Offset 0Ch-0Fh Reserved. Read/Write 0s. OwnershipChange. This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. 29:7 Reserved. Read/Write 0s. AMD Geode™ SC3200 Processor Data Book HcRevision Register (RO) HcControl Register (R/W) HcCommandStatus Register (R/W) HcInterruptStatus Register (R/W)
  • Page 286 1: Disable interrupt generation due to Ownership Change. 29:7 Reserved. Read/Write 0s. Core Logic Module - USB Controller Registers - PCIUSB HcInterruptEnable Register (R/W) HcInterruptDisable Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value = 00000000h Reset Value = 00000000h...
  • Page 287 BulkCurrentED. Pointer to the current Bulk List ED. Reserved. Read/Write 0s. Offset 30h-33h 31:4 DoneHead. Pointer to the current Done List Head ED. Reserved. Read/Write 0s. AMD Geode™ SC3200 Processor Data Book HcHCCA Register (R/W) HcPeriodCurrentED Register (R/W) HcControlHeadED Register (R/W) HcControlCurrentED Register (R/W) HcBulkHeadED Register (R/W)
  • Page 288 HcFrameRemaining Register (RO) HcFmNumber Register (RO) HcPeriodicStart Register (R/W) HcLSThreshold Register (R/W) HcRhDescriptorA Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value = 00002EDFh Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000000h Reset Value = 00000628h...
  • Page 289 Write: ClearGlobalPower. Writing a 1 issues a ClearGlobalPower command to the ports. Writing a 0 has no effect. Note: This register is reset by the UsbReset state. AMD Geode™ SC3200 Processor Data Book HcRhDescriptorB Register (R/W) HcRhStatus Register (R/W) 32581C...
  • Page 290 1: Port is selectively suspended. Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect. Core Logic Module - USB Controller Registers - PCIUSB HcRhPortStatus[1] Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value = 00000000h...
  • Page 291 0: Port reset signal is not active. 1: Port reset signal is active. Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect. AMD Geode™ SC3200 Processor Data Book HcRhPortStatus[2] Register (R/W) 32581C Reset Value = 00000000h...
  • Page 292 0: Full speed device. 1: Low speed device. Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect. Core Logic Module - USB Controller Registers - PCIUSB HcRhPortStatus[3] Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value = 00000000h...
  • Page 293 HceStatus is 0, IRQ1 is generated: if 1, then an IRQ12 is generated. CharacterPending. When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is set to 0. AMD Geode™ SC3200 Processor Data Book Reserved HceControl Register (R/W)
  • Page 294 This register is the emulation side of the legacy Status register. Core Logic Module - USB Controller Registers - PCIUSB HceInput Register (R/W) HceOutput Register (R/W) HceStatus Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value = 000000xxh Reset Value = 000000xxh Reset Value = 00000000h...

  • Page 295: Table 6-43. Dma Channel Control Registers

    Channel 3 Terminal Count. Indicates if TC was reached. 0: No. 1: Yes. AMD Geode™ SC3200 Processor Data Book • DMA Page Registers, see Table 6-44 • Programmable Interval Timer Registers, see Table 6-45 • Programmable Interrupt Controller Registers, see Table 6-46 •...
  • Page 296 0: Not masked. 1: Masked. Channel Number Mask Select. 00: Channel 0. 01: Channel 1. 10: Channel 2. 11: Channel 3. Core Logic Module - ISA Legacy Register Space DMA Command Register, Channels 3:0 AMD Geode™ SC3200 Processor Data Book...
  • Page 297 I/O Port 0CCh Not supported. I/O Port 0CEh Not supported. AMD Geode™ SC3200 Processor Data Book DMA Channel 4 Address Register (R/W) DMA Channel 4 Transfer Count Register (R/W) DMA Channel 5 Address Register (R/W) DMA Channel 5 Transfer Count Register (R/W)
  • Page 298 0: Normal. 1: Compressed. Channels 7:4. 0: Disable. 1: Enable. Reserved. Must be set to 0. Core Logic Module - ISA Legacy Register Space DMA Status Register, Channels 7:4 DMA Command Register, Channels 7:4 AMD Geode™ SC3200 Processor Data Book...
  • Page 299 DMA Master Clear Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. I/O Port 0DCh DMA Clear Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not supported. AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 300 DMA Channel 1 High Page Register (R/W) DMA Channel 0 High Page Register (R/W) DMA Channel 6 High Page Register (R/W) DMA Channel 7 High Page Register (R/W) DMA Channel 5 High Page Register (R/W) AMD Geode™ SC3200 Processor Data Book...

  • Page 301: Table 6-45. Programmable Interval Timer Registers

    11: R/W LSB, followed by MSB. Current Counter Mode. 0-5. BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). AMD Geode™ SC3200 Processor Data Book PIT Timer 0 Counter PIT Timer 0 Status PIT Timer 1 Counter (Refresh) PIT Timer 1 Status (Refresh)
  • Page 302 Current Counter Mode. 0-5. BCD Mode. 0: Binary. 1: BCD (Binary Coded Decimal). Core Logic Module - ISA Legacy Register Space PIT Timer 2 Counter (Speaker) PIT Timer 2 Status (Speaker) PIT Mode Control Word Register AMD Geode™ SC3200 Processor Data Book...

  • Page 303: Table 6-46. Programmable Interrupt Controller Registers

    IRQ4 / IRQ12 Mask. 0: Not Masked. 1: Mask. IRQ3 / IRQ11 Mask. 0: Not Masked. 1: Mask. AMD Geode™ SC3200 Processor Data Book Master / Slave PIC ICW1 (WO) Master / Slave PIC OCW1 (except immediately after ICW1 is written) 32581C...
  • Page 304 100: Set rotate in Auto EOI mode 101: Rotate on non-specific EOI command 110: Set priority command (bits [2:0] must be valid) 111: Rotate on specific EOI command Master / Slave PIC OCW3 (WO) for OCW3 Commands (RO) AMD Geode™ SC3200 Processor Data Book...
  • Page 305 1: Yes. IRQ3 / IRQ11 In-Service. 0: No. 1: Yes. IRQ2 / IRQ10 In-Service. 0: No. 1: Yes. IRQ1 / IRQ9 In-Service. 0: No. 1: Yes. IRQ0 / IRQ8 In-Service. 0: No. 1: Yes. AMD Geode™ SC3200 Processor Data Book 32581C...

  • Page 306: Table 6-47. Keyboard Controller Registers

    This bit must be cleared before the generation of another reset. Core Logic Module - ISA Legacy Register Space Port B Control Register (R/W) Port A Control Register (R/W) AMD Geode™ SC3200 Processor Data Book Reset Value: 00x01100b Reset Value: 02h...

  • Page 307: Table 6-48. Real-Time Clock Registers

    1: Level. IRQ4 Edge or Level Sensitive Select. Selects PIC IRQ4 sensitivity configuration. 0: Edge. 1: Level. AMD Geode™ SC3200 Processor Data Book Table 6-48. Real-Time Clock Registers RTC Address Register (WO) RTC Data Register (R/W) RTC Extended Address Register (WO) RTC Data Register (R/W) Table 6-49.
  • Page 308 IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration. 0: Edge. 1: Level. Reserved. Must be set to 0. Interrupt Edge/Level Select Register 2 (R/W) Core Logic Module - ISA Legacy Register Space Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 309: 7.0Video Processor Module

    • YUV-to-RGB color space conversion • Horizontal filtering and downscaling • Supports 4:2:2, 4:2:0 YUV formats and RGB 5:6:5 format AMD Geode™ SC3200 Processor Data Book 7.0Video Processor Module Graphics-Video Overlay and Blending • Overlay of video up to 16 bpp •...

  • Page 310: Module Architecture

    The following subsections describe each block in detail. Video Formatter Horizontal Downscaler, Video Line Buffer, Horizontal Data Video and Vertical Upscalers, and Filters Mixer/Blender Overlay with Gamma RAM and Alpha Blending AMD Geode™ SC3200 Processor Data Book Video Processor Module TFT_IF...

  • Page 311: Functional Description

    This method is known as Capture Video mode. How each mode is setup and operates is explained further in Section 7.2.1 on page 313. AMD Geode™ SC3200 Processor Data Book 32581C VBI Support VBI (vertical blanking interval) data is placed in the video data stream during a portion of the vertical retrace period.

  • Page 312: Figure 7-2. Ntsc 525 Lines, 60 Hz, Odd Field

    Active Video Logical Line 24 — Scan Lines 287-525 Vertical Retrace - Logical Line 24 — Scan Line 264 (Not normally User Data) Video Processor Module VSYNC Start VSYNC End VSYNC Start VSYNC End AMD Geode™ SC3200 Processor Data Book...

  • Page 313: Figure 7-4. Vip Block Diagram

    Data CCIR-656 Decoder Clock Direct Video/VBI AMD Geode™ SC3200 Processor Data Book Video data is clocked out using the GX1’s Video port clock (75, 116, or 133 MHz GX1 core clock divided by 2 or 4). 7.2.1.1 Direct Video Mode...
  • Page 314 The new address will not take affect until the start of a new display con- troller frame. The field that was just received can be known reading Current F4BAR2+Memory Offset 08h[24]. AMD Geode™ SC3200 Processor Data Book Field...

  • Page 315: Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer

    Weave method. Since at least double buffering is required, more of the VIP’s control registers are used for Weave than required for Bob during video runtime. AMD Geode™ SC3200 Processor Data Book Video Data Even Base (F4BAR2+Memory Offset 24h) Address not changed during runtime...

  • Page 316: Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers

    Video Frame Buffer #2 Line 1 Odd Field Line 1 Even Field Line 2 Odd Field Line 2 Even Field Line n-1 Odd Field Line n-1 Even Field Line n Odd Field Line n Even Field AMD Geode™ SC3200 Processor Data Book...

  • Page 317: Figure 7-7. Video Block Diagram

    Video Module 4-Tap Horizontal Video Input Downscaler Formatter AMD Geode™ SC3200 Processor Data Book RGB 5:6:5 – For this format each pixel is described as a 16-bit value: Bits [15:11] = Red Bits [10:5] = Green Bits [4:0] = Blue YUV 4:2:0 –...

  • Page 318: Figure 7-8. Horizontal Downscaler Block Diagram

    (F4BAR0+Memory Offset 3Ch) selects the type of down- scaling factor to be used. Note: There is no vertical downscaling in the Video Pro- cessor. Bypass 4-Tap Horizontal Filtering Downscaler Downscale Factors Video Processor Module Video Downscaler Control To Line Buffers AMD Geode™ SC3200 Processor Data Book register...

  • Page 319: Figure 7-9. Linear Interpolation Calculation

    YUV 4:4:4 format. RGB data is not translated. There is no direct program control of the Formatter. i+1,j Figure 7-9. Linear Interpolation Calculation AMD Geode™ SC3200 Processor Data Book 7.2.2.5 2-Tap Vertical and Horizontal Upscalers After the video data has been buffered, the upscaling algo- rithm can be applied.

  • Page 320: Figure 7-10. Mixer/Blender Block Diagram

    GV_GAMMA_SEL * /GAMMA_EN Optional Gamma Correction Color/Chroma 1/2 Y Mixer/Blender Flicker Filter RGB to Cursor Color Key Compare Compare Color/Chroma Key Video Processor Module CRT DACs and TFT Interface Key and YUV Data TVOUT Block AMD Geode™ SC3200 Processor Data Book...

  • Page 321: Table 7-1. Valid Mixing/Blending Configurations

    01h. The address 01h would contain the data 02h and so on. This would have the effect of increasing each original Red, Green, and Blue value by one. AMD Geode™ SC3200 Processor Data Book Mode Comment Input: YUV Progressive Video •...

  • Page 322: Figure 7-11. Graphics/Video Frame With Alpha Windows

    (see Section 5.5.3 “Hardware Cursor” in the AMD Geode™ GX1 Pro- cessor Data Book). When the software cursor is used, the cursor size and position are not defined using registers.

  • Page 323: Table 7-2. Truth Table For Alpha Blending

    ALPHAx_COLOR_REG_EN = 1 = 1) Window x ALPHAx_COLOR_REG_EN = 0 COLOR_CHROMA_SEL: F4BAR0+Memory Offset 04h[20]. GFX_INS_VIDEO: F4BAR0+Memory Offset 4Ch[8]. ALPHAx_COLOR_REG_EN: F4BAR0+Memory Offsets 68h[24], 78h[24], and 88h[24]. AMD Geode™ SC3200 Processor Data Book Graphics Data Match Cursor Configuration Color Key GFX_INS_VIDEO = 0...

  • Page 324: Figure 7-12. Color Key And Alpha Blending Logic

    Pixel value matches normal color COLOR_CHROMA _SEL = 1 window Use graphics value for this pixel Video Processor Module COLOR_CHROMA _SEL = 1 Use video value Use graphics for this pixel value for this pixel AMD Geode™ SC3200 Processor Data Book...

  • Page 325: Figure 7-13. Tft Power Sequence

    FP_PWR_EN FP_VDD_ON TFTD[17:0], HSYNC, VSYNC, TFTDE, TFTDCK AMD Geode™ SC3200 Processor Data Book • TFTDCK - data clock signal. • TFTDE - data enable signal. • FP_VDD_ON - power control signal Power Sequence Power sequence is used to control assertion of FP_VDD_ON and TFTD signals.

  • Page 326: Figure 7-14. Pll Block Diagram

    2Ch[19:16]), if the crystal oscillator has a frequency of 27 MHz. This PLL can be powered down via the Miscella- neous register (F4BAR0+Memory Offset 28h[12]). Phase Charge Loop Pump Filter Divider Figure 7-14. PLL Block Diagram Video Processor Module register (F4BAR0+Memory Offset Divide AMD Geode™ SC3200 Processor Data Book...

  • Page 327: Register Descriptions

    1Ch-1Fh Palette Address Register 20h-23h Palette Data Register 24h-27h Reserved AMD Geode™ SC3200 Processor Data Book 32581C 7.3.1 Register Summary The tables in this subsection summarize the registers of the Video Processor. Included in the tables are the regis- ter’s reset values and page references where the bit for- mats are found.
  • Page 328 00000000h Page 342 001B0017h Page 343 00000000h Page 343 Page 343 00000000h Page 343 00000000h Page 343 00000000h Page 343 00000000h Page 343 00000000h Page 344 00000000h Page 344 Page 344 1FFF1FFFh Page 344 AMD Geode™ SC3200 Processor Data Book...

  • Page 329: Table 7-5. F4Bar2: Vip Support Registers Summary

    2Ch-3Fh Reserved 40h-43h VBI Data Odd Base Register 44h-47h VBI Data Even Base Register 48h-4Bh VBI Data Pitch Register 4Ch-1FFh Reserved AMD Geode™ SC3200 Processor Data Book 32581C Reset Reference Value (Table 7-8) 00000000h Page 345 00000000h Page 345 xxxxxxxxh...

  • Page 330: Table 7-6. F4: Pci Header Registers For Video Processor Support Registers

    Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h Reset Value: 100Bh Reset Value: 0504h Reset Value: 00h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...
  • Page 331 This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INTA#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively. Index 3Eh-FFh AMD Geode™ SC3200 Processor Data Book Interrupt Pin Register (R/W) Reserved...

  • Page 332: Table 7-7. F4Bar0+Memory Offset: Video Processor Configuration Registers

    Video Configuration Register (R/W) 10: Y0 Cb Y1 Cr 11: Y0 Cr Y1 Cb 10: Y1 Y0 Y3 Y2 11: Y1 Y2 Y3 Y0 10: P1M P1L P2M P2L 11: P1M P2L P2M P1L Reset Value: 00000000h AMD Geode™ SC3200 Processor Data Book...
  • Page 333 TFT_EN (TFT Enable). Enables the TFT control logic and is also used to reset the TFT control logic. 0: Reset TFT control logic. 1: Enable TFT control logic. AMD Geode™ SC3200 Processor Data Book Display Configuration Register (R/W) 32581C Reset Value: x0000000h...
  • Page 334 H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. 31:28 Reserved.
  • Page 335 When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional DOTCLK period. This effect should go unnoticed during normal operation. Reserved. Offset 24h-27h AMD Geode™ SC3200 Processor Data Book Video Color Key Register (R/W) Video Color Mask Register (R/W) Reserved...
  • Page 336 1000: 65 1100: 108 1001: 75 1101: 135 1010: 78.5 1110: 27 1011: 94.5 1111: 24.923052 Reserved Reserved Reserved AMD Geode™ SC3200 Processor Data Book Reset Value: 00001400h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h...
  • Page 337 31:16 Reserved. 15:8 REV_ID (Revision ID). See the AMD Geode™ SC3200 Specification Update document for value. DEV_ID (Device ID). See the AMD Geode™ SC3200 Specification Update document for value. AMD Geode™ SC3200 Processor Data Book Video Downscaler Control Register (R/W)
  • Page 338 Mixing and blending configurations are created using bits [13,11:9] of this register. See Table 7-1 "Valid Mixing/ Blending Configurations" on page 321. Video Processor Module - Video Processor Registers - Function 4 AMD Geode™ SC3200 Processor Data Book Reset Value: 00060000h...
  • Page 339 This is one of two possible cursor color values. The COLOR_REG_OFFSET bits (F4BAR0+Memory Offset 50h[28:24]) determine a bit of the graphics data that if even, selects this color to be used. AMD Geode™ SC3200 Processor Data Book Cursor Color Key Register (R/W)
  • Page 340 (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 341 (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 342 H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some- times referred to as “horizontal back porch”. For more information, see the AMD Geode™ GX1 Processor Data Book. Note: Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
  • Page 343 The GX1 module’s video clock must be active at all times, regardless of the source of video input. Offset 404h-407h Offset 408h-40Bh 31:0 Reserved. Offset 40Ch-41Fh AMD Geode™ SC3200 Processor Data Book Video Request Register (R/W) Alpha Watch Register (RO) Reserved Video Processor Display Mode Register (R/W) Reserved...
  • Page 344 CGENTO0 (Odd Field Continuous GenLock Timeout). Video Processor Module - Video Processor Registers - Function 4 GenLock Register (R/W) GenLock Delay Register (R/W) Reserved Continuous GenLock Timeout Register (R/W) Reset Value: 00000000h Reset Value: 00000000h Reset Value: 1FFF1FFFh AMD Geode™ SC3200 Processor Data Book...

  • Page 345: Table 7-8. F4Bar2+Memory Offset: Vip Configuration Registers

    Interrupt generation can be enabled regardless of whether or not video capture (store to memory) is enabled. 0: Disable. 1: Enable. 15:11 Reserved. Must be set to 0. AMD Geode™ SC3200 Processor Data Book are located. Table 7-8 shows the memory mapped VIP sup- port registers accessed through F4BAR2. Video Interface Control Register (R/W) 32581C...
  • Page 346 0: VBI data is not being stored to memory. 1: VBI data is now being stored to memory. Video Processor Module - Video Processor Registers - Function 4 Video Interface Status Register (R/W) Reset Value: xxxxxxxxh AMD Geode™ SC3200 Processor Data Book...
  • Page 347 31:16 Reserved. 15:0 Video Data Pitch. Specifies the logical width of the video data buffer. Bits [1:0] are always 0. Offset 2Ch-3Fh AMD Geode™ SC3200 Processor Data Book Reserved Video Current Line Register (RO) Video Line Target Register (R/W) Reserved...
  • Page 348 Video Processor Module - Video Processor Registers - Function 4 VBI Data Odd Base Register (R/W) VBI Data Even Base Register (R/W) VBI Data Pitch Register (R/W) Reserved Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00000000h Reset Value: 00h AMD Geode™ SC3200 Processor Data Book...

  • Page 349: 8.0Debugging And Monitoring

    EXTEST SAMPLE/PRELOAD IDCODE CLAMP Reserved Reserved BYPASS AMD Geode™ SC3200 Processor Data Book 8.0Debugging and Monitoring 8.1.2 Optional Instruction Support The TAP supports the following IEEE optional instructions: • IDCODE Presents the contents of the Device Identification register in serial format.
  • Page 350 32581C Debugging and Monitoring AMD Geode™ SC3200 Processor Data Book...

  • Page 351: 9.0Electrical Specifications

    Note 2. No bias. Note 3. Voltage min is -0.8V with a transient voltage of 20 ns or less. Note 4. Voltage max is 4.0V with a transient voltage of 20 ns or less. AMD Geode™ SC3200 Processor Data Book 9.0Electrical Specifications 9.1.2...

  • Page 352: Table 9-3. Operating Conditions

    Electrical Specifications Unit Comments 3.46 3.46 3.46 1.99 3.46 3.46 1.99 (Output Low Current) op- be less than 0.25V, in order to reduce be less than 0.25V, in order to reduce AMD Geode™ SC3200 Processor Data Book...

  • Page 353: Table 9-4. Power Planes Of External Interface Signals

    • Sleep (SL2): This is the lowest power state the SC3200 can be in with voltage still applied to the device’s core and I/O supply pins. This is equivalent to the ACPI spec- ification’s “S1” state. AMD Geode™ SC3200 Processor Data Book 32581C Balls CCUSB 9.1.5.2...

  • Page 354: Table 9-5. System Conditions Used To Measure Sc3200 Current During On State

    = 3.3V CORE CORE = 1.8V (Nominal); = 2.0V (Nominal); Electrical Specifications DCLK SDRAM Frequency Frequency 50 MHz (Note 2) Nominal 135 MHz (Note 3) Abs Max Unit Comments for V for V CORE 1090 AMD Geode™ SC3200 Processor Data Book...

  • Page 355: Table 9-7. Dc Characteristics For Active Idle, Sleep, And Off States

    Output Pin Capacitance Pin Inductance Note 1. T = 25°C, f = 1 MHz. All capacitances are not 100% tested. Note 2. Not 100% tested. AMD Geode™ SC3200 Processor Data Book = 3.3V = 3.3V CORE CORE = 1.8V (Nominal);...

  • Page 356: Pull-Up And Pull-Down Resistors

    22.5K D10, N30 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K A9, N31 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 22.5K 100K AJ6, AK5, 100K 22.5K AMD Geode™ SC3200 Processor Data Book...

  • Page 357: Dc Characteristics

    Output, TRI-STATE, capable of sourcing p mA and sinking n mA WIRE Wire, no buffer Note 1.Output from these signals is open-drain and cannot be forced high. AMD Geode™ SC3200 Processor Data Book The subsections that follows provide detailed DC charac- teristics according to buffer type. Table 9-10. Buffer Types is 0.6V...
  • Page 358 µA µA - not IN Unit 0.5V +0.3 (Note 1) -0.5 0.3V (Note 1) 0.7V +/-10 µA AMD Geode™ SC3200 Processor Data Book Electrical Specifications Comments Comments Comments Note 2 0 < V < V , Note 3, Note 4...
  • Page 359 Note 1. Not 100% tested. 9.2.7 DC Characteristics Symbol Parameter Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Note 1. Not 100% tested. AMD Geode™ SC3200 Processor Data Book Unit 0.6V +0.3 (Note 1) 0.3V µA −10 µA Unit +0.3...

  • Page 360: Figure 9-1. Differential Input Sensitivity For Common Mode Range

    (Note 1) Common Mode Input Voltage (volts) 0.9V 0.1V Electrical Specifications Unit Comments µA µA |(D+)-(D-)| and Figure 9-1 Includes V Range Unit Comments = -5 mA = 5 mA Unit Comments = n mA AMD Geode™ SC3200 Processor Data Book...
  • Page 361 Signals with internal pull-ups have a maximum input leakage current of: Where V is V , or V power Signals with internal pull-downs have a maximum input leakage current of: AMD Geode™ SC3200 Processor Data Book Unit 0.1V Unit Unit 0.9V 0.1V...

  • Page 362: Ac Characteristics

    Output Low Drive Voltage All AC tests are at V C to 85 C, C Valid Output Valid Input AMD Geode™ SC3200 Processor Data Book Electrical Specifications Value (V) = 3.14V to 3.46V (3.3V nominal), = 50 pF, unless otherwise specified.

  • Page 363: Memory Controller Interface

    INPUTS Legend: A = Maximum Output Delay B = Minimum Output Delay C = Minimum Input Setup D = Minimum Input Hold Figure 9-3. Memory Controller Drive Level and Measurement Points AMD Geode™ SC3200 Processor Data Book Valid Output 32581C...

  • Page 364: Table 9-12. Memory Controller Timing Parameters

    SHFTSDCLK field, and y is 0.45 the core clock period. Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the AMD Geode™ GX1 Proces- sor Data Book for more information.

  • Page 365: Figure 9-4. Memory Controller Output Valid Timing Diagram

    SDCLK[3:0] Control Output, MA[12:0] BA[1:0], MD[63:0] Figure 9-4. Memory Controller Output Valid Timing Diagram SDCLK_IN MD[63:0] Data Valid Read Data In Figure 9-5. Read Data In Setup and Hold Timing Diagram AMD Geode™ SC3200 Processor Data Book 32581C Data Valid...

  • Page 366: Figure 9-6. Video Input Port Timing Diagram

    VPCKIN fall/rise time VPCK_FR VPCKIN duty cycle VPCK_D Note 1. Guaranteed by characterization. VPCKIN PCK_FR VPD[7:0] Figure 9-6. Video Input Port Timing Diagram Unit 35/65 VP_C PCK_FR VP_S VP_H AMD Geode™ SC3200 Processor Data Book Electrical Specifications Comments Note 1...

  • Page 367: Figure 9-7. Tft Timing Diagram

    TFTDCK period time (multiplexed on CLK_P Parallel Port) TFTDCK duty cycle CLK_D Note 1. Guaranteed by characterization TFTDCK TFTD[17:0] TFTDE AMD Geode™ SC3200 Processor Data Book Table 9-14. TFT Timing Parameters 12.5 40/60 CLK_P Figure 9-7. TFT Timing Diagram 32581C Unit Comments...

  • Page 368: Table 9-15. Access.bus Input Timing Parameters

    Note 2 μs Before Stop condition, Note 2 μs After Start condition, Note 2 μs Before Start condition, Note 2 μs Before AB1C/AB2C rising edge, Note 2 μs Before AB1C/AB2C rising edge, Note 2 μs AMD Geode™ SC3200 Processor Data Book...

  • Page 369: Figure 9-8. Acb Signals: Rising Time And Falling Timing Diagram

    Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram AB1D AB2D DLCs DLCo AB1C AB2C Figure 9-9. ACB Start and Stop Condition Timing Diagram AMD Geode™ SC3200 Processor Data Book SCLfo 0.7V 0.3V SDAr 0.7V 0.3V SCLr Stop Condition...

  • Page 370: Figure 9-10. Acb Start Condition Timing Diagram

    Figure 9-10. ACB Start Condition Timing Diagram AB1D AB2D AB1C AB2C SDAvo SDAho Figure 9-11. ACB Data Bit Timing Diagram Start Condition DHCsi CSTRsi CSTRhi DHCso CSTRso CSTRho SDAsi SDAso SCLlowi SCLlowo AMD Geode™ SC3200 Processor Data Book Electrical Specifications SDAhi SDAho SCLhighi SCLhigho...

  • Page 371: Pci Bus Interface

    Output Buffer Figure 9-12. Testing Setup for Slew Rate and Minimum Timing AMD Geode™ SC3200 Processor Data Book All parameters in Table 9-17 are not 100% tested. The parameters in this table are further described in Figure 9- Table 9-17. PCI AC Specifications -12V -17.1(V...

  • Page 372: Figure 9-13. V/I Curves For Pci Output Signals

    >V >0.7V Figure 9-13. V/I Curves for PCI Output Signals Output Voltage Volts Test Point Drive Point Drive Point -48V +0.4V = (256/V Electrical Specifications Pull-Down 0.5V Test Point Equation B for 0V<V <0.18V AMD Geode™ SC3200 Processor Data Book...

  • Page 373: Figure 9-14. Pciclk Timing And Measurement Points

    Note 4. The minimum PCIRST# slew rate applies only to the rising (de-assertion) edge of the reset signal. See Figure 9-18 for PCIRST# timing. 0.5 V 0.4 V PCICLK 0.3 V Figure 9-14. PCICLK Timing and Measurement Points AMD Geode™ SC3200 Processor Data Book Table 9-18. PCI Clock Parameters 0.6V 0.2V HIGH 32581C Unit...

  • Page 374: Figure 9-15. Load Circuits For Maximum Time Measurements

    Note 1, Note 3, Note 1, Note 3, Note 4 Note 4 Note 4 Note 3, Note 5 µs Note 3, Note 5 Note 3, Note 5, Note 6 (Max) Falling Edge 0.5" max. Ω 10 pF AMD Geode™ SC3200 Processor Data Book...

  • Page 375: Figure 9-16. Output Timing Measurement Conditions

    Note 2. V specifies the maximum peak-to-peak waveform allowed for measuring input timing. PCICLK Output Delay TRI-STATE Output Figure 9-16. Output Timing Measurement Conditions AMD Geode™ SC3200 Processor Data Book Value Unit 0.6 V 0.2 V 0.4 V 0.285 V 0.615 V 0.4 V...

  • Page 376: Figure 9-17. Input Timing Measurement Conditions

    Note: The value of t is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than FAIL 500 mV. TEST Input Valid TEST RST-CLK Figure 9-18. PCI Reset Timing Electrical Specifications TEST FAIL RST-OFF AMD Geode™ SC3200 Processor Data Book...

  • Page 377: Table 9-21. Sub-Isa Timing Parameters

    MEMW#/WR#/DOCW# hold after IOCHRDY RE IOCHRDY valid after IOR#/MEMR#/ RDYA1 RD#/DOCR#/IOW#/MEMW#/WR#/ DOCW# FE AMD Geode™ SC3200 Processor Data Book The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 9-21. Sub-ISA Timing Parameters Width (Bits)
  • Page 378 8, 16 M, I/O 8, 16 8, 16 M, I/O 8, 16 M, I/O 8, 16 M, I/O 8, 16 M, I/O AMD Geode™ SC3200 Processor Data Book Electrical Specifications Figure Comments 9-19 9-20 9-19 9-20 9-19 9-20 9-19 9-19...

  • Page 379: Figure 9-19. Sub-Isa Read Operation Timing Diagram

    MEMW#/DOCW# D[15:0] (Read) D[15:0] (Write) IOCHRDY RDYAx Note: x indicates a numeric index for the relevant symbol. Figure 9-19. Sub-ISA Read Operation Timing Diagram AMD Geode™ SC3200 Processor Data Book IOCSA IOCSH Valid RVDS Valid Data RDYH 32581C Valid RCUx...

  • Page 380: Figure 9-20. Sub-Isa Write Operation Timing Diagram

    MEMW#/DOCW# TRDE# D[15:0] IOCHRDY IOR#/RD# MEMR#/DOCR# Note: x indicates a numeric index for the relevant symbol. Figure 9-20. Sub-ISA Write Operation Timing Diagram IOCSA Valid Valid Data RDYAx RDYH Electrical Specifications IOCSH Valid WCUx AMD Geode™ SC3200 Processor Data Book...

  • Page 381: Figure 9-21. Lpc Output Timing Diagram

    Input Hold time PCICLK LPC Signals/ SERIRQ Figure 9-21. LPC Output Timing Diagram PCICLK LPC Signals/ SERIRQ AMD Geode™ SC3200 Processor Data Book Unit Input Valid Figure 9-22. LPC Input Timing Diagram 32581C Comments After PCICLK rising edge After PCICLK rising edge...

  • Page 382: Ide Interface

    IDE signals rise time (from 0.1V IDE_RISE IDE_RST# pulse width IDE_RST_PW IDE_RST# to 0.1V to 0.9V IDE_RST_PW Figure 9-23. IDE Reset Timing Diagram Electrical Specifications Unit Comments = 40 pF = 40 pF µs AMD Geode™ SC3200 Processor Data Book...

  • Page 383: Table 9-24. Ide Register Transfer To/From Device Timing Parameters

    If the device is not driving IDE_IORDY[0:1] negated after activation (t is met and t is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (t IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t AMD Geode™ SC3200 Processor Data Book Mode 1250 1250...

  • Page 384: Figure 9-24. Register Transfer To/From Device Timing Diagram

    IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t . IDE_IORDY[0:1] is released prior to negation and may be asserted for no before asserting IDE_IORDY[0:1]. Electrical Specifications . IDE_IORDY[0:1] is AMD Geode™ SC3200 Processor Data Book...

  • Page 385: Table 9-25. Ide Pio Data Transfer To/From Device Timing Parameters

    If the device is not driving IDE_IORDY[0:1] negated after the activation (t then t is met and t is not applicable. If the device is driving IDE_IORDY[0:1] negated after the activation (t IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t AMD Geode™ SC3200 Processor Data Book Mode 1250 1250 1250...

  • Page 386: Figure 9-25. Pio Data Transfer To/From Device Timing Diagram

    IDE_IOR[0:1]# or IDE_IOW[0:1]#. but causes IDE_IORDY[0:1] to be asserted before t . IDE_IORDY[0:1] is released prior to negation and may be asserted for no before asserting IDE_IORDY[0:1]. Electrical Specifications . IDE_IORDY[0:1] is AMD Geode™ SC3200 Processor Data Book...

  • Page 387: Table 9-26. Ide Multiword Dma Data Transfer Timing Parameters

    KR/KW data.) AMD Geode™ SC3200 Processor Data Book Mode is the minimum command active time, and t and t and t . (This means that a host implementation can lengthen t KR/KW is equal to or greater than the value reported in the device’s IDENTIFY DEVICE...

  • Page 388: Figure 9-26. Multiword Dma Data Transfer Timing Diagram

    IDE_DREQ[0:1] asserted and wait for the host to reasse IDE_DACK[0:1]#. This signal can be negated by the host to Suspend the DMA transfer in process. Figure 9-26. Multiword DMA Data Transfer Timing Diagram Electrical Specifications AMD Geode™ SC3200 Processor Data Book...

  • Page 389: Table 9-27. Ide Ultradma Data Burst Timing Parameters

    (either sender or recipient) is wait- ing for the other agent to respond with a signal before proceeding. t is a limited timeout with a defined minimum. t AMD Geode™ SC3200 Processor Data Book Mode 0 Mode 1 is an unlimited interlock with no maximum time value.

  • Page 390: Figure 9-27. Initiating An Ultradma Data In Burst Timing Diagram

    (DSTROBE[0:1]) signal lines are not in effect until IDE_REQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-27. Initiating an UltraDMA Data in Burst Timing Diagram negation of DMARDY. Both STROBE and DMARDY timing measurements are taken at the connector of the sender. after the ZIORDY Electrical Specifications AMD Geode™ SC3200 Processor Data Book...

  • Page 391: Figure 9-28. Sustained Ultradma Data In Burst Timing Diagram

    Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram AMD Geode™ SC3200 Processor Data Book 2CYC 2CYC...

  • Page 392: Figure 9-29. Host Pausing An Ultradma Data In Burst Timing Diagram

    IDE_IOR[0:1]# (HDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the host may receive up to two additional data WORDs from the device. Figure 9-29. Host Pausing an UltraDMA Data In Burst Timing Diagram Electrical Specifications AMD Geode™ SC3200 Processor Data Book...

  • Page 393: Figure 9-30. Device Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-30. Device Terminating an UltraDMA Data In Burst Timing Diagram AMD Geode™ SC3200 Processor Data Book 32581C IORDZ...

  • Page 394: Figure 9-31. Host Terminating An Ultradma Data In Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted. Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram IORDYZ AMD Geode™ SC3200 Processor Data Book Electrical Specifications...

  • Page 395: Figure 9-32. Initiating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are not in effect until IDE_DREQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC3200 Processor Data Book ZIORDY 32581C...

  • Page 396: Figure 9-33. Sustained Ultradma Data Out Burst Timing Diagram

    Figure 9-33. Sustained UltraDMA Data Out Burst Timing Diagram 2CYC 2CYC Electrical Specifications AMD Geode™ SC3200 Processor Data Book...

  • Page 397: Figure 9-34. Device Pausing An Ultradma Data Out Burst Timing Diagram

    IDE_IORDY[0:1]# (DDMARDY[0:1]#) is de-asserted. If the t timing is not satisfied, the device may receive up to two additional datawords from the host. Figure 9-34. Device Pausing an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC3200 Processor Data Book 32581C after...

  • Page 398: Figure 9-35. Host Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram Electrical Specifications IORDYZ AMD Geode™ SC3200 Processor Data Book...

  • Page 399: Figure 9-36. Device Terminating An Ultradma Data Out Burst Timing Diagram

    Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-36. Device Terminating an UltraDMA Data Out Burst Timing Diagram AMD Geode™ SC3200 Processor Data Book IORDZ 32581C...

  • Page 400: Universal Serial Bus (Usb) Interface

    (Monotonic) from 90% to 10% of the D_Port lines Average bit rate 1.5 Mbps ± 1.5% μs at 1.5 Mbps Host (downstream), Note 4 9-38 Host (downstream), Note 4 9-38 Function (downstream), Note 4 AMD Geode™ SC3200 Processor Data Book...
  • Page 401 Note 4. Measured at the crossover point of differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3). Note 5. EOP is the End of Packet where DPOS_PORT (Min). Note 6. C = 350 pF. AMD Geode™ SC3200 Processor Data Book 32581C Unit Figure Comments –150 9-38 μs...

  • Page 402: Figure 9-37. Data Signal Rise And Fall Timing Diagram

    Data Lines = 350 pF USB_DJ11 USB_DJD21 USB_DJU21 Crossover Points (1.3-2.0) V USB_DJ11 USB_DJD21 USB_DJU21 Paired Transitions period_F USB_DJ12 period_L USB_DJD22 period_L USB_DJU22 Electrical Specifications Rise Time Fall Time USB_R1,2 USB_F1,2 USB_DJ12 USB_DJD22 USB_DJU22 AMD Geode™ SC3200 Processor Data Book...

  • Page 403: Figure 9-39. Eop Width Timing Diagram

    Figure 9-39. EOP Width Timing Diagram period_F period_L Differential Data Lines Consecutive Transitions period_F period_L period_L Figure 9-40. Receiver Jitter Tolerance Timing Diagram AMD Geode™ SC3200 Processor Data Book Data Crossover Level Source: USB_SE1, USB_DE1 Receiver: USB_DE2 USB_RE11, USB_RE21,...

  • Page 404: Serial Port (Uart)

    (Note 1) 1.48 1.78 ± 0.87% ± 2.0% ± 2.5% ± 6.5% Electrical Specifications Unit Comments Transmitter Receiver Transmitter Receiver Transmitter Receiver + 15 Transmitter, Variable µs Transmitter, Fixed µs Receiver Transmitter Receiver Transmitter Receiver AMD Geode™ SC3200 Processor Data Book...

  • Page 405: Figure 9-42. Fast Ir (Mir And Fir) Timing Diagram

    MIR mode. It is determined by the M_PWID field (bits [4:0]) in the MIR_PW register at offset 01h in bank 6 of logical device 5. Figure 9-42. Fast IR (MIR and FIR) Timing Diagram AMD Geode™ SC3200 Processor Data Book (Note 1) ± 0.1% ±...

  • Page 406: Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram

    Note 1. Times are system dependent and are therefore not tested. BUSY ACK# PD[7:0] STB# Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram Unit AMD Geode™ SC3200 Processor Data Book Electrical Specifications Comments Note 1 Note 1 Note 1...

  • Page 407: Figure 9-44. Enhanced Parallel Port Timing Diagram

    EPDW PD[7:0] hold after DSTRB# or EPDH ASTRB# inactive WW19a WRITE# DSTRB# ASTRB# WST19a PD[7:0] WPDS WAIT# Figure 9-44. Enhanced Parallel Port Timing Diagram AMD Geode™ SC3200 Processor Data Book WPDH WEST WW19ia 32581C Unit Comments WST19a EPDH Valid EPDW...

  • Page 408: Figure 9-45. Ecp Forward Mode Timing Diagram

    ECHHF BUSY inactive after STB# active ECHLF STB# active after BUSY inactive ECLLF PD[7:0] AFD# STB# BUSY Figure 9-45. ECP Forward Mode Timing Diagram ECDHF ECDSF ECHLF ECLHF ECHHF AMD Geode™ SC3200 Processor Data Book Electrical Specifications Unit Comments ECLLF...

  • Page 409: Figure 9-46. Ecp Reverse Mode Timing Diagram

    ACK# inactive after AFD# inactive ECHHR AFD# active after ACK# inactive ECHLR ACK# active after AFD# active ECLLR PD[7:0] BUSY# ACK# AFD# Figure 9-46. ECP Reverse Mode Timing Diagram AMD Geode™ SC3200 Processor Data Book ECDSR ECHLR ECLHR ECHHR 32581C Unit Comments ECDHR ECLLR...

  • Page 410: Figure 9-47. Ac97 Reset Timing Diagram

    SYNC active high pulse width SYNC_HIGH SYNC inactive to BIT_CLK startup SYNC_IA delay SYNC BIT_CLK Figure 9-48. AC97 Sync Timing Diagram 162.8 RST2CLK RST_LOW 162.8 SYNC_IA SYNC_HIGH AMD Geode™ SC3200 Processor Data Book Electrical Specifications Unit Comments µs Unit Comments µs...

  • Page 411: Figure 9-49. Ac97 Clocks Diagram

    AC97_CLK fall/rise time AC97_CLK_FR AC97_CLK output edge-to- AC97_CLK_J edge jitter Note 1. Worst case duty cycle restricted to 40/60. BIT_CLK SYNC AC97_CLK AMD Geode™ SC3200 Processor Data Book Table 9-37. AC97 Clocks Parameters 12.288 81.4 32.56 40.7 48.84 32.56 40.7 48.84...

  • Page 412: Figure 9-50. Ac97 Data Timing Diagram

    Sync out hold after falling edge of AC97_SH BIT_CLK BIT_CLK SDATA_OUT/SYNC SDATA_IN, SDATA_IN2 Table 9-38. AC97 I/O Timing Parameters 15.0 10.0 AC97_SV AC97_OV AC97_S AC97_H Figure 9-50. AC97 Data TIming Diagram Electrical Specifications Unit Comments AC97_SH AC97_OH AMD Geode™ SC3200 Processor Data Book...

  • Page 413: Figure 9-51. Ac97 Rise And Fall Timing Diagram

    SDATA_IN fall time trise SDATA_OUT rise time DOUT tfall SDATA_OUT fall time DOUT BIT_CLK SYNC SDATA_IN SDATA_OUT Figure 9-51. AC97 Rise and Fall Timing Diagram AMD Geode™ SC3200 Processor Data Book Unit trise tfall trise tfall SYNC SYNC trise tfall trise tfall...

  • Page 414: Figure 9-52. Ac97 Low Power Mode Timing Diagram

    End of Slot 2 to BIT_CLK, s2_pdown SDATA_IN low SYNC BIT_CLK SDATA_OUT SDATA_IN Note: BIT_CLK is not to scale Figure 9-52. AC97 Low Power Mode Timing Diagram Unit µs Slot 1 Slot 2 s2_pdown AMD Geode™ SC3200 Processor Data Book Electrical Specifications Comments...

  • Page 415: Figure 9-53. Pwrbtn# Trigger And Onctl# Timing Diagram

    Table 9-42. Power Management Event (GPWIO) and ONCTL# Timing Parameters Symbol Parameter Power management event to ONCTL# assertion GPWIOx ONCTL# PWRCNT1 PWRCNT2 Figure 9-54. GPWIO and ONCTL# Timing Diagram AMD Geode™ SC3200 Processor Data Book Unit PBTNP PBTNE PBTNE Unit 32581C Comments Note 1 PBTNP...

  • Page 416: Figure 9-55. Power-Up Sequencing With Pwrbtn# Timing Diagram

    V If PWRBTN# max is exceeded, ONCTL# will go inactive. System determines when V and V are applied, hence there is no maximum constraint. POR# must not glitch during active time. AMD Geode™ SC3200 Processor Data Book CORE...

  • Page 417: Figure 9-56. Power-Up Sequencing Without Pwrbtn# Timing Diagram

    Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low. AMD Geode™ SC3200 Processor Data Book -100...

  • Page 418: Jtag Interface

    Non-test inputs setup time TDI, TMS hold time Non-test inputs hold time IH(Min) 1.5V IL(Max) Figure 9-57. TCK Measurement Points and Timing Diagram Table 9-45. JTAG Timing Parameters Electrical Specifications Unit Comments 50 pF load AMD Geode™ SC3200 Processor Data Book...

  • Page 419: Figure 9-58. Jtag Test Timing Diagram

    Electrical Specifications TDI, Output Signals Input Signals AMD Geode™ SC3200 Processor Data Book Figure 9-58. JTAG Test Timing Diagram 32581C...
  • Page 420 32581C Electrical Specifications AMD Geode™ SC3200 Processor Data Book...

  • Page 421: 10.0Package Specifications

    (Nominal) Frequency Power (W) 1.8V 266 MHz AMD Geode™ SC3200 Processor Data Book 10.0Package Specifications ) of the pack- A maximum junction temperature is not specified since a maximum case temperature is. Therefore, the following equation can be used to calculate the maximum thermal...

  • Page 422: Figure 10-1. Heatsink Example

    SC3200 processor, which is always less than 4 Watts. CA = 45/9 = 5 Package Specifications (max) = 40°C. − T 85 − 40 =8). (max) = 40°C. − T 85 − 40 AMD Geode™ SC3200 Processor Data Book...

  • Page 423: Physical Dimensions

    Package Specifications 32581C 10.2 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-Terminal Ball Grid Array Cavity Up) package. Figure 10-2. BGU481 Package - Top View AMD Geode™ SC3200 Processor Data Book...

  • Page 424: Figure 10-3. Bgu481 Package - Bottom View

    32581C Package Specifications Figure 10-3. BGU481 Package - Bottom View AMD Geode™ SC3200 Processor Data Book...

  • Page 425: A.1 Order Information

    The “F” suffix denotes the Pb-free (lead-free) package. See Section 10.0 on page 421 for the BGU481 (481-terminal Ball Grid Array Cavity Up) package specification. Consult your local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations possibly not listed.

  • Page 426: Data Book Revision History

    32581C Data Book Revision History This document is a report of the revision/creation process of the data book for the AMD Geode™ SC3200 processor. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Revision #...
  • Page 427 Appendix A: Data Book Revision History Table A-1. Revision History (Continued) Revision # (PDF Date) Revisions / Comments Table 9-3 "Operating Conditions" on page 352: Change maximum VCORE and VSBL values from (February 2007) 1.89V to 1.99V. AMD Geode™ SC3200 Processor Data Book 32581C...
  • Page 428 One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306...

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