Sign In
Upload
Manuals
Brands
AMD Manuals
Computer Hardware
Geode SC1200
AMD Geode SC1200 Manuals
Manuals and User Guides for AMD Geode SC1200. We have
1
AMD Geode SC1200 manual available for free PDF download: Data Book
AMD Geode SC1200 Data Book (443 pages)
Processor
Brand:
AMD
| Category:
Computer Hardware
| Size: 3.58 MB
Table of Contents
Table of Contents
3
List of Figures
5
List of Tables
9
1 0Overview
13
General Description
13
Figure 1-1. Block Diagram
13
Features
14
2 0Architecture Overview
17
GX1 Module
17
Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary
18
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers
18
Video Processor Module
22
Core Logic Module
22
Superi/O Module
23
Clock, Timers, and Reset Logic
23
3 0Signal Definitions
25
Figure 3-1. Signal Groups
25
Ball Assignments
27
Table 3-1. Signal Definitions Legend
27
Figure 3-2. BGU481 Ball Assignment Diagram
28
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
29
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name
40
Strap Options
44
Table 3-4. Strap Options
44
Multiplexing Configuration
45
Table 3-5. Two-Signal/Group Multiplexing
45
Table 3-6. Three-Signal/Group Multiplexing
47
Table 3-7. Four-Signal/Group Multiplexing
48
Signal Descriptions
49
Table 6-44. DMA
61
4 0General Configuration Block
71
Configuration Block Addresses
71
Table 4-1. General Configuration Block Register Summary
71
Pin Multiplexing, Interrupt Selection, and Base Address Registers
72
Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers
72
Watchdog
79
Figure 4-1. WATCHDOG Block Diagram
79
Table 4-3. WATCHDOG Registers
80
High-Resolution Timer
81
Table 4-4. High-Resolution Timer Registers
82
Clock Generators and Plls
83
Figure 4-2. Clock Generation Block Diagram
83
Figure 4-3. Recommended Oscillator External Circuitry
84
Table 4-5. Crystal Oscillator Circuit Components
84
Table 4-6. Core Clock Frequency
85
Table 4-7. Strapped Core Clock Frequency
85
Table 4-8. Clock Generator Configuration
87
5 0Superi/O Module
89
Figure 5-1. SIO Block Diagram
89
Features
90
Module Architecture
91
Figure 5-2. Detailed SIO Block Diagram
91
Configuration Structure / Access
92
Figure 5-3. Standard Configuration Register File Structure
92
Table 5-1. SIO Configuration Options
92
Table 5-2. LDN Assignments
92
Standard Configuration Registers
94
Figure 5-4. Standard Configuration Registers Map
94
Table 5-3. Standard Configuration Registers
95
Table 5-4. SIO Control and Configuration Register Map
97
Table 5-5. SIO Control and Configuration Registers
97
Table 5-6. Relevant RTC Configuration Registers
98
Table 5-7. RTC Configuration Registers
99
Table 5-8. Relevant SWC Registers
100
Table 5-9. Relevant IRCP/SP3 Registers
101
Table 5-10. IRCP/SP3 Configuration Register
101
Table 5-11. Relevant Serial Ports 1 and 2 Registers
102
Table 5-12. Serial Ports 1 and 2 Configuration Register
102
Table 5-13. Relevant ACB1 and ACB2 Registers
103
Table 5-14. ACB1 and ACB2 Configuration Register
103
Table 5-15. Relevant Parallel Port Registers
104
Table 5-16. Parallel Port Configuration Register
104
Real-Time Clock (RTC)
105
Figure 5-5. Recommended Oscillator External Circuitry
105
Table 5-17. Crystal Oscillator Circuit Components
105
Figure 5-6. External Oscillator Connections
106
Figure 5-7. Divider Chain Control
106
Figure 5-8. Power Supply Connections
108
Figure 5-9. Typical Battery Configuration
108
Figure 5-10. Typical Battery Current: Battery Backed Power Mode @ T C = 25°C
108
Figure 5-11. Typical Battery Current: Normal Operation Mode
108
Table 5-18. System Power States
109
Figure 5-12. Interrupt/Status Timing
110
Table 5-19. RTC Register Map
111
Table 5-20. RTC Registers
111
Table 5-21. Divider Chain Control / Test Selection
114
Table 5-22. Periodic Interrupt Rate Encoding
114
Table 5-23. BCD and Binary Formats
114
Table 5-24. Standard RAM Map
115
Table 5-25. Extended RAM Map
115
System Wakeup Control (SWC)
116
Table 5-26. Time Range Limits for CEIR Protocols
116
Table 5-27. Banks 0 and 1 - Common Control and Status Register Map
117
Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
117
Table 5-29. Banks 0 and 1 - Common Control and Status Registers
118
Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
119
Access.bus Interface
121
Figure 5-13. Bit Transfer
121
Figure 5-14. Start and Stop Conditions
121
Figure 5-15. Access.bus Data Transaction
122
Figure 5-16. Access.bus Acknowledge Cycle
122
Figure 5-17. a Complete Access.bus Data Transaction
123
Table 5-31. ACB Register Map
126
Table 5-32. ACB Registers
126
Legacy Functional Blocks
129
Table 5-33. Parallel Port Register Map for First Level Offset
129
Table 5-34. Parallel Port Register Map for Second Level Offset
129
Table 5-35. Parallel Port Bit Map for First Level Offset
130
Table 5-36. Parallel Port Bit Map for Second Level Offset
130
Figure 5-18. UART Mode Register Bank Architecture
131
Table 5-37. Bank 0 Register Map
131
Table 5-38. Bank Selection Encoding
132
Table 5-39. Bank 1 Register Map
132
Table 5-40. Bank 2 Register Map
132
Table 5-41. Bank 3 Register Map
132
Table 5-42. Bank 0 Bit Map
133
Table 5-43. Bank 1 Bit Map
133
Table 5-44. Bank 2 Bit Map
134
Table 5-45. Bank 3 Bit Map
134
Figure 5-19. IRCP/SP3 Register Bank Architecture
135
Table 5-46. Bank 0 Register Map
135
Table 5-47. Bank Selection Encoding
136
Table 5-48. Bank 1 Register Map
136
Table 5-49. Bank 2 Register Map
136
Table 5-50. Bank 3 Register Map
137
Table 5-51. Bank 4 Register Map
137
Table 5-52. Bank 5 Register Map
137
Table 5-53. Bank 6 Register Map
138
Table 5-54. Bank 7 Register Map
138
Table 5-55. Bank 0 Bit Map
138
Table 5-56. Bank 1 Bit Map
139
Table 5-57. Bank 2 Bit Map
139
Table 5-58. Bank 3 Bit Map
139
Table 5-59. Bank 4 Bit Map
139
Table 5-60. Bank 5 Bit Map
140
Table 5-61. Bank 6 Bit Map
140
Table 5-62. Bank 7 Bit Map
140
6 0Core Logic Module
141
Feature List
141
Module Architecture
142
Figure 6-1. Core Logic Module Block Diagram
142
Table 6-1. Physical Region Descriptor Format
145
Table 6-2. Ultradma/33 Signal Definitions
146
Figure 6-2. Non-Posted Fast-PCI to ISA Access
148
Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled
149
Figure 6-4. ISA DMA Read from PCI Memory
150
Figure 6-5. ISA DMA Write to PCI Memory
150
Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
151
Figure 6-6. PCI Change to Sub-ISA and Back
152
Figure 6-7. PIT Timer
154
Figure 6-8. PIC Interrupt Controllers
155
Table 6-4. PIC Interrupt Mapping
155
Figure 6-9. PCI and IRQ Interrupt Mapping
156
Figure 6-10. SMI Generation for NMI
157
Table 6-5. Wakeup Events Capability
159
Table 6-6. Power Planes Control Signals Vs. Sleep States
160
Table 6-7. Power Planes Vs. Sleep/Global States
160
Table 6-8. Power Management Events
160
Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
165
Table 6-9. Device Power Management Programming Summary
166
Table 6-10. Bus Masters that Drive Specific Slots of the AC97 Interface
167
Table 6-11. Physical Region Descriptor Format
168
Figure 6-12. PRD Table Example
169
Figure 6-13. AC97 V2.0 Codec Signal Connections
170
Figure 6-14. Audio SMI Tree Example
172
Figure 6-15. Typical Setup
173
Table 6-12. Cycle Types
174
Register Descriptions
175
Table 6-13. PCI Configuration Address Register (0Cf8H)
175
Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary
176
Table 6-15. F0BAR0: GPIO Support Registers Summary
179
Table 6-16. F0BAR1: LPC Support Registers Summary
179
Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
180
Table 6-18. F1BAR0: SMI Status Registers Summary
180
Table 6-19. F1BAR1: ACPI Support Registers Summary
181
Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
182
Table 6-21. F2BAR4: IDE Controller Support Registers Summary
183
Table 6-22. F3: PCI Header Registers for Audio Support Summary
183
Table 6-23. F3BAR0: Audio Support Registers Summary
184
Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
185
Table 6-25. F5BAR0: I/O Control Support Registers Summary
185
Table 6-26. PCIUSB: USB PCI Configuration Register Summary
186
Table 6-27. USB_BAR: USB Controller Registers Summary
187
Table 6-28. ISA Legacy I/O Register Summary
188
Chipset Register Space
190
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support
190
Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers
224
Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
228
Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support
236
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers
237
Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers
247
Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
256
Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
260
Table 6-37. F3: PCI Header Registers for Audio Configuration
262
Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers
263
Table 6-39. F5: PCI Header Registers for X-Bus Expansion
277
Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
281
Table 6-41. PCIUSB: USB PCI Configuration Registers
283
Table 6-42. Usb_Bar+Memory Offset: USB Controller Registers
285
Table 6-43. DMA Channel Control Registers
296
Table 6-45. Programmable Interval Timer Registers
302
Table 6-46. Programmable Interrupt Controller Registers
304
Table 6-47. Keyboard Controller Registers
307
Table 6-48. Real-Time Clock Registers
308
Table 6-49. Miscellaneous Registers
308
7 0Video Processor Module
311
Module Architecture
312
Figure 7-1. Video Processor Block Diagram
312
Functional Description
313
Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
314
Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
314
Figure 7-4. VIP Block Diagram
315
Table 7-1. Direct Mode and Capture Mode Configurations
316
Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer
317
Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
319
Figure 7-7. Video Block Diagram
320
Figure 7-8. Horizontal Downscaler Block Diagram
321
Figure 7-9. Linear Interpolation Calculation
322
Figure 7-10. Mixer/Blender Block Diagram
323
Table 7-2. Valid Mixing/Blending Configurations
324
Figure 7-11. Graphics/Video Frame with Alpha Windows
326
Table 7-3. Truth Table for Alpha Blending
327
Figure 7-12. Color Key and Alpha Blending Logic
328
Figure 7-13. TVOUT Block Diagram
329
Table 7-4. Flicker Filter Operation
329
Figure 7-14. DAC Voltage Levels
330
Figure 7-15. TFT Power Sequence
331
Figure 7-16. PLL Block Diagram
332
Register Descriptions
333
Table 7-5. F4: PCI Header Registers for Video Processor Support Summary
333
Table 7-6. F4BAR0: Video Processor Configuration Registers Summary
333
Table 7-7. F4BAR2: VIP Support Registers Summary
335
Table 7-8. F4: PCI Header Registers for Video Processor Support Registers
336
Table 7-9. F4Bar0+Memory Offset: Video Processor Configuration Registers
338
Table 7-10. F4Bar2+Memory Offset: VIP Configuration Registers
359
8 0Debugging and Monitoring
363
Testability (JTAG)
363
Table 8-1. JTAG Mode Instruction Support
363
9 0Electrical Specifications
365
General Specifications
365
Table 9-1. Electro Static Discharge (ESD)
365
Table 9-2. Absolute Maximum Ratings
365
Table 9-3. Operating Conditions
366
Table 9-4. Power Planes of External Interface Signals
367
Table 9-5. System Conditions Used to Measure SC1200/SC1201 Current During on State
368
Table 9-6. DC Characteristics for on State
368
Table 9-7. DC Characteristics for Active Idle, Sleep, and off States
369
Table 9-8. Ball Capacitance and Inductance
369
Table 9-9. Balls with PU/PD Resistors
370
DC Characteristics
371
Table 9-10. Buffer Types
371
Figure 9-1. Differential Input Sensitivity for Common Mode Range
374
AC Characteristics
376
Figure 9-2. General Drive Level and Measurement Points
376
Table 9-11. Default Levels for Measurement of Switching Parameters
376
Figure 9-3. Memory Controller Drive Level and Measurement Points
377
Table 9-12. Memory Controller Timing Parameters
378
Figure 9-4. Memory Controller Output Valid Timing Diagram
379
Figure 9-5. Read Data in Setup and Hold Timing Diagram
379
Figure 9-6. Video Input Port Timing Diagram
380
Table 9-13. Video Input Port Timing Parameters
380
Figure 9-7. Video Output Port Timing Diagram
381
Table 9-14. Video Output Port Timing Parameters
381
Figure 9-8. TFT Timing Diagram
382
Table 9-15. TFT Timing Parameters
382
Table 9-16. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs)
383
Table 9-17. TV DAC (4 Outputs: CVBS, SVY/TVR, SVC/TVB, CVBS/TVG)
384
Table 9-18. Access.bus Input Timing Parameters
385
Table 9-19. Access.bus Output Timing Parameters
385
Figure 9-9. ACB Signals: Rising and Falling Timing Diagram
386
Figure 9-10. ACB Start and Stop Condition Timing Diagram
386
Figure 9-11. ACB Start Condition Timing Diagram
387
Figure 9-12. ACB Data Bit Timing Diagram
387
Figure 9-13. Testing Setup for PCI Slew Rate and Minimum Timing
388
Table 9-20. PCI AC Specifications
388
Figure 9-14. V/I Curves for PCI Output Signals
389
Figure 9-15. PCICLK Timing and Measurement Points
390
Table 9-21. PCI Clock Parameters
390
Figure 9-16. Load Circuits for PCI Maximum Time Measurements
391
Table 9-22. PCI Timing Parameters
391
Figure 9-17. PCI Output Timing Measurement Conditions
392
Table 9-23. Measurement Condition Parameters
392
Figure 9-18. PCI Input Timing Measurement Conditions
393
Figure 9-19. PCI Reset Timing
393
Table 9-24. Sub-ISA Timing Parameters
394
Figure 9-20. Sub-ISA Read Operation Timing Diagram
396
Figure 9-21. Sub-ISA Write Operation Timing Diagram
397
Figure 9-22. LPC Output Timing Diagram
398
Figure 9-23. LPC Input Timing Diagram
398
Table 9-25. LPC and SERIRQ
398
Figure 9-24. IDE Reset Timing Diagram
399
Table 9-26. IDE General Timing Parameters
399
Table 9-27. IDE Register Transfer To/From Device Timing Parameters
400
Figure 9-25. Register Transfer To/From Device Timing Diagram
401
Table 9-28. IDE PIO Data Transfer To/From Device Timing Parameters
402
Figure 9-26. PIO Data Transfer To/From Device Timing Diagram
403
Table 9-29. IDE Multiword DMA Data Transfer Timing Parameters
404
Figure 9-27. Multiword DMA Data Transfer Timing Diagram
405
Table 9-30. IDE Ultradma Data Burst Timing Parameters
406
Figure 9-28. Initiating an Ultradma Data in Burst Timing Diagram
407
Figure 9-29. Sustained Ultradma Data in Burst Timing Diagram
408
Figure 9-30. Host Pausing an Ultradma Data in Burst Timing Diagram
409
Figure 9-31. Device Terminating an Ultradma Data in Burst Timing Diagram
410
Figure 9-32. Host Terminating an Ultradma Data in Burst Timing Diagram
411
Figure 9-33. Initiating an Ultradma Data out Burst Timing Diagram
412
Figure 9-34. Sustained Ultradma Data out Burst Timing Diagram
413
Figure 9-35. Device Pausing an Ultradma Data out Burst Timing Diagram
414
Figure 9-36. Host Terminating an Ultradma Data out Burst Timing Diagram
415
Figure 9-37. Device Terminating an Ultradma Data out Burst Timing Diagram
416
Table 9-31. USB Timing Parameters
417
Figure 9-38. USB Data Signal Rise and Fall Timing Diagram
419
Figure 9-39. USB Source Differential Data Jitter Timing Diagram
419
Figure 9-40. USB EOP Width Timing Diagram
420
Figure 9-41. USB Receiver Jitter Tolerance Timing Diagram
420
Figure 9-42. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
421
Table 9-32. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters
421
Figure 9-43. Fast IR Timing (mir and FIR) Diagram
422
Table 9-33. Fast IR Port Timing Parameters
422
Figure 9-44. Standard Parallel Port Typical Data Exchange Timing Diagram
423
Table 9-34. Standard Parallel Port Timing Parameters
423
Figure 9-45. Enhanced Parallel Port Timing Diagram
424
Figure 9-46. ECP Forward Mode Timing Diagram
425
Table 9-36. ECP Forward Mode Timing Parameters
425
Figure 9-47. ECP Reverse Mode Timing Diagram
426
Table 9-37. ECP Reverse Mode Timing Parameters
426
Figure 9-48. AC97 Reset Timing Diagram
427
Figure 9-49. AC97 Sync Timing Diagram
427
Table 9-38. AC Reset Timing Parameters
427
Table 9-39. AC97 Sync Timing Parameters
427
Figure 9-50. AC97 Clocks Diagram
428
Table 9-40. AC97 Clocks Parameters
428
Figure 9-51. AC97 Data Timing Diagram
429
Table 9-41. AC97 I/O Timing Parameters
429
Figure 9-52. AC97 Rise and Fall Timing Diagram
430
Table 9-42. AC97 Signal Rise and Fall Timing Parameters
430
Figure 9-53. AC97 Low Power Mode Timing Diagram
431
Table 9-43. AC97 Low Power Mode Timing Parameters
431
Figure 9-54. PWRBTN# Trigger and ONCTL# Timing Diagram
432
Figure 9-55. GPWIO and ONCTL# Timing Diagram
432
Table 9-44. PWRBTN# Timing Parameters
432
Table 9-45. Power Management Event (GPWIO) and ONCTL# Timing Parameters
432
Figure 9-56. Power-Up Sequencing with PWRBTN# Timing Diagram
433
Table 9-46. Power-Up Sequence Using the Power Button Timing Parameters
433
Figure 9-57. Power-Up Sequencing Without PWRBTN# Timing Diagram
434
Table 9-47. Power-Up Sequence Not Using the Power Button Timing Parameters
434
Figure 9-58. TCK Measurement Points and Timing Diagram
435
Table 9-48. JTAG Timing Parameters
435
Figure 9-59. JTAG Test Timing Diagram
436
10 0Package Specifications
437
Thermal Characteristics
437
Table 10-1. Q JC (×C/W)
437
Table 10-2. Case-To-Ambient Thermal Resistance Example @ 85×C
437
Figure 10-1. Heatsink Example
438
Physical Dimensions
439
Figure 10-2. BGU481 Package - Top View
439
Figure 10-3. BGU481 Package - Bottom View
440
Appendix A Support Documentation
441
Order Information
441
A.1 Order Information
441
Macrovision Product Notice
441
Data Book Revision History
442
Table A-1. Revision History
442
Advertisement
Advertisement
Related Products
AMD Geode SC1201
AMD Geode SC2200
AMD Geode SC3200
AMD Sempron 10
AMD SB600
AMD SP5100
AMD SB710
AMD Geode LX 600@0.7W
AMD Geode LX 700@0.8W
AMD Geode LX 800@0.9W
AMD Categories
Video Card
Computer Hardware
Motherboard
Microcontrollers
Software
More AMD Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL