Table 2-8 Ide Device Registers Mapping - AMD SB600 Technical Reference Manual

Field Name
Bus Master IDE
Start/Stop
Reserved
Bus Master Read/Write
Reserved
Bus-master IDE Status Register
Address Offset:
Field Name
Bus Master Active
Bus Master DMA Error
IDE Interrupt
Reserved
Master Device DMA
Capable
Slave Device DMA
Capable
Simplex Only
Descriptor Table Pointer Register
Address Offset:
Field Name
Reserved
Descriptor Table Base
Address
Address (hex)
Compatibility Mode
IDE Command Block Registers
Primary
1F0 Base Address 0 + 0
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bus-master IDE Command - RW- 8 bits - [IDE:00h]
Bits Default
0 0b Bus Master IDE Start (1)/Stop (0).
This bit will not be reset by interrupt from IDE device. This must
be reset by soft ware (device driver).
2:1 0h Reserved. Wired 0's.
3 0b Bus Master IDE r/w (direction) control
0 = Memory -> IDE
1 = IDE -> Memory
This bit should not change during Bus Master transfer cycle, even
if terminated by Bus Master IDE stop.
7:4 0h Reserved. These bits are always read as 0's.
Primary – Base + 02h
Bus-master IDE Status - RW- 8 bits - [IDE:02h]
Bits Default
0 0b Bus Master IDE active. This bit is set to 1 when bit 0 in the Bus
Master IDE command address register is set to 1. The IDE host
controller sets this bit to 0 when the last transfer for a region is
performed. This bit is also set to 0 when bit 0 of the Bus Master
IDE command register is set to 0.
1 0b IDE DMA error. This bit is set when the IDE host controller
encounters a target abort, master abort, or Parity error while
transferring data on the PCI bus. Software sets this bit to a 0, by
writing a 1 to it.
2 0b IDE Interrupt. Indicates when an IDE device has asserted its
interrupt line. IRQ14 is used for the primary channel. If the
interrupt status bit is set to 0, by writing a 1 to this bit while the
interrupt line is still at the active level, this bit remains 0 until
another assertion edge is detected on the interrupt line.
4:3 0h Reserved. Always read as 0's.
5 0b Device 0 (Master) DMA capable.
6 0b Device 1 (Slave) DMA capable.
7 0b Simplex only. This bit is hard-wired as 0.
Primary – Base + 04h
Bus-master IDE Command - RW- 32 bits - [IDE:04h]
Bits Default
1:0 0h
31:2 0000_0000h
Address [31-02].

Table 2-8 IDE Device Registers Mapping

Native Mode (Offset)
Data (16 bit)
Description
Description
Description
Reserved. Always read as 0's.
Base Address of Descriptor Table. These bits correspond to
Name and Function
Read Function
Data (16 bit)
IDE Controller (Device 20, Function 1)
Proprietary
Write Function
Page 196