AMD SB600 Technical Reference Manual page 216

Subsystem ID & Subsystem Vendor ID - W/R - 32 bits - [PCI_Reg: 2Ch]
Field Name
Subsystem Vendor ID
Subsystem ID
This 4-byte register is a write-once & read-only afterward register. The BIOS writes to this register once (all 4 bytes
at once) & software reads its value when needed.
Field Name
Capabilities Pointer
Field Name
Interrupt Line
Field Name
Interrupt Pin
Field Name
Min_Gnt
Field Name
Max_Lat
MSI Capability Register Set IDs- R – 16 bits - [PCI_Reg: 40h]
Field Name
Capability ID
Pointer to Next ID
MSI Message Control Register- RW - 16 bits - [PCI_Reg: 42h]
Field Name
MSI Enable
Multiple Message
Capable
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
15:0 0000h
31:16 0000h
Capabilities Pointer - R - 8 bits - [PCI_Reg: 34h]
Bits Default
7:0 40h
Interrupt Line - RW - 8 bits - [PCI_Reg: 3Ch]
Bits Default
7:0 00h
Interrupt Pin - R - 8 bits - [PCI_Reg: 3Dh]
Bits Default
7:0 02h
Min_Gnt - R - 8 bits - [PCI_Reg: 3Eh]
Bits Default
7:0 02h
Min_Gnt - R - 8 bits - [PCI_Reg: 3Fh]
Bits Default
7:0 00h
Bits Default
7:0 05h Read only. 05h indicates it is an MSI capability register set.
15:8 00h Read only. 00h indicates there is no additional register set.
Bits Default
0 0b 0 - Function Is disabled from using MSI.
1 - Function is enabled to use MSI.
3:1 0b Hardwired to 0 to indicate the device would like 1 message
allocated to it.
Description
Subsystem Vendor ID.
Subsystem ID.
Description
Read only. Indicates that the device has New Capabilities
register set starting at address 40h.
Description
Identifies which input on the interrupt controller the
function's PCI interrupt request pin (as specified in its
Interrupt Pin register) is routed to.
Description
Hard-wired to 2 to indicate that this function (modem
controller) uses interrupt pin INTB# on PCI bus.
Description
The value hardwired into this register indicates how long the
bus master would like to retain PCI bus ownership.
Description
This read-only register specifies how often the device needs
access to the PCI bus (in increments of 250ns).
Description
Description
AC '97 Controller Functional Descriptions
Proprietary Page 216