Hd Audio Controller Memory Mapped Registers - AMD SB600 Technical Reference Manual

MSI Message Lower Address – RW - 32 bits – [PCI_Reg: 64h]
Field Name
MSI Message Lower
Address
Reserved
MSI Message Upper Address – RW - 32 bits – [PCI_Reg: 68h]
Field Name
MSI Message Upper
Address
Field Name
MSI Message Data
2.6.2

HD Audio Controller Memory Mapped Registers

The base memory location for these memory mapped registers is specified in the PCI Configuration Upper
and Lower Base Address Registers. The individual registers are then accessible at Base + offset as
indicated in the following table. These registers are accessed in byte, word, or dword quantities.
Output Stream Payload Capability
Immediate Command Output Interface
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
31:2 00000000
h
01:0 0h
Bits Default
31:0 00000000
h
MSI Message Data – RW - 16 bits – [PCI_Reg: 6Ch]
Bits Default
15:0 0000h
Register Name
Global Capabilities
Minor Version
Major Version
Output Payload Capability
Input Payload Capability
Global Control
Wake Enable
State Change Status
Global Status
Input Stream Payload Capability
Interrupt Control
Interrupt Status
Wall Clock Counter
Stream Synchronization
CORB Lower Base Address
CORB Upper Base Address
CORB Write Pointer
CORB Read Pointer
CORB Control
CORB Status
CORB SIze
RIRB Lower Base Address
RIRB Upper Address
RIRB Write Pointer
RIRB Response Interrupt Control
RIRB Control
RIRB Status
RIRB Size
Description
Lower Address used for MSI Message.
Reserved
Description
Upper Address used for MSI Message.
Description
Data used for MSI Message.
Proprietary
Address Offset
00h
02h
03h
04h
06h
08h
0Ch
0Eh
10h
18h
1Ah
20h
24h
30h
38h
40h
44h
48h
4Ah
4Ch
4Dh
4Eh
50h
54h
58h
5Ah
5Ch
5Dh
5Eh
60h
HD Audio Controllers Registers
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