Acpi Registers - AMD SB600 Technical Reference Manual

2.3.3.3

ACPI Registers

* Note: The offset addresses listed here for the ACPI registers belong to different apertures/decodes. Check the register
descriptions for details.
Field Name
TmrStatus
Reserved
BmStatus
GblStatus
Reserved
PwrBtnStatus
Reserved
RtcStatus
Reserved
PciExpWakeStatus
WakeStatus
This register is located at the base address defined by AcpiPmEvtBlk.
Field Name
TmrEn
Reserved
GblEn
Reserved
PwrBtnEn
Reserved
RtcEn
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
Pm1Status
Pm1Enable
PmControl
PmaControl
TmrValue/ETmrValue
CLKVALUE
PLvl2
PLvl3
PLvl4
AcpiSsCnt
EVENT_STATUS
EVENT_ENABLE
Pm1Status - RW - 16 bits - [AcpiPmEvtBlk:00h]
Bits Default
0 0b Timer carry status bit. This bit gets set anytime the 23
bit of 24/32 bit counter changes (whenever the MSB changes
from low to high or high to low. While TmrEn and TmrStatus
are set, an interrupt event is raised). [Read-only]
3:1 000b
4 0b Bus master status bit. This bit is set any time a system bus
master requests the system bus, and can only be cleared by
writing an one to this bit position.
5 0b This bit is set when an SCI is generated due to the BIOS
wanting the attention of the SCI handler. This is set by writing
1 to PM_Reg: 0Eh bit [1].
7:6 00b
8 0b Power button status bit
9 0b
10 0b This bit is set when RTC generates an alarm.
13:11 000b
14 0b This bit is set by hardware to indicate that the system woke
due to a PCI Express wakeup event.
15 0b This bit is set when the system is in the sleep state and a
wake-up event occurs.
Pm1Enable - RW - 16 bits - [AcpiPmEvtBlk:02h]
Bits Default
0 0b This is the timer carry interrupt enable bit. When this bit is
set then an SCI event is generated anytime the TmrStatus is
set. When this bit is reset then no interrupt is generated
when the TmrStatus bit is set.
4:1 0h
5 0b If this bit is set, SCI is raised whenever both GblEn and
GblStatus are true.
7:6 00b
8 0b If this bit is set, SCI is generated whenever PwrBtnStatus is
true.
9 0b
10 0b RTC enable. If this bit is set, SCI is generated whenever
RtcStatus is true.
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Offset Address*
00h
02h
00h
00h
00h
00h
04h
05h
06h
00h
00h
04h
rd st
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