AMD SB600 Technical Reference Manual page 251

Field Name
SERR# Enable
Fast Back-tp-Back Enable
Reserved
Command Register: The PCI specification defines this register to control a PCI device's ability to generate and
respond to PCI cycles.
Field Name
Reserved
Capabilities List
Reserved
Master Data Parity
Error
Device Select Timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
Status Register: The PCI specification defines this register to record status information for PCI related events.
Writing 0 to a bit has no effect; writing 1 to a bit will clear it to 0.
Field Name
Revision ID
Class Code
Revision ID/Class Code Register: This read only register contains the device's revision information and generic
function. Since SB600 is an ISA bridge, its assigned class code is 060100h.
Field Name
Cache Line Size
Cache Line Size Register: This register specifies the system cache line size. This register is not implemented.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
CMD- RW - 16 bits - [PCI_Reg: 04h]
Bits Default
8 0b
9 0b
15:10 00h
STATUS- RW - 16 bits - [PCI_Reg: 06h]
Bits Default
3:0 0h
4 0b This bit is read only. When reg0x78[1] is 1, this bit reads 1; when
reg0x78[1] is 0, this bit reads 0. This is to satisfy K8
requirement. For P4 system, 0x78[1] should be set to 0 to mask
off this bit.
7:5 0h
8 0h Data Parity reported – Set to 1 if the LPC bridge detects PERR#
asserted while acting as PCI master (whether PERR# was driven
by the LPC bridge or not.)
10:9 1h DEVSEL# timing – Read only bits indicating DEVSEL# timing
when performing a positive decode.
Since DEVSEL# is asserted to meet the medium timing, these
bits are encoded as 01b.
11 0b Signaled Target Abort – This bit is set to 1 when the LPC bridge
signals Target Abort.
12 0b Received Target Abort – This bit is set to 1 when the LPC bridge
-generated PCI cycle is aborted by a PCI target. Cleared by
writing a 1 to it.
13 0b Received Master Abort Status. Set to 1 when the LPC bridge
acts as a PCI master and aborts a PCI bus cycle. Cleared by
writing a 1 to this bit.
14 0b SERR# status. This bit is set to 1, when the LPC bridge detects
a system error.
15 0b Detected Parity Error. This bit is set to 1 when the LPC bridge
detects a parity error.
Revision ID/Class Code - R - 8 bits - [PCI_Reg: 08h]
Bits Default
7:0 00h These bits are hardwired to 00h to indicate the revision level of
the chip design
31:8 060100h Class Code.
Cache Line Size - R - 8 bits - [PCI_Reg: 0Ch]
Bits Default
7:0 00h Cache Line Size.
Description
SERR# enable - If set to 1, the LPC bridge asserts SERR#
when it detects as address parity error. SERR# is not
asserted if this bit is 0.
Hardcoded to 0 to indicate that Fast Back-to-back is
disabled. The LPC bridge only acts as a master to a single
device, so this functionality is not needed.
Description
Description
Description
LPC ISA Bridge (Device 20, Function 3)
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