Indirect Access Registers - AMD SB600 Technical Reference Manual

4.5.2

Indirect Access Registers

Software needs to first select the register to access using the IO Register Select Register, and then read or
write using the IO Window Register.
Field Name
<reserved>
ID
<reserved>
Not used in XAPIC PCI bus delivery mode.
IOXAPIC Version Register [Indirect Address Offset = 01H] R
Field Name
Version
<Reserved>
PRQ
Max Redirection Entries
<Reserved>
IOAPIC Arbitration Register [Indirect Address Offset = 02H] R
Field Name
<reserved>
Arbitration ID
<reserved>
Not used in XAPIC PCI bus delivery mode.
Redirection Table Entry [0–23] [Indirect Address Offset = 11/10H–3F/3EH] RW
Field Name
Vector
Delivery Mode
Destination Mode
Delivery Status
Interrupt Pin Polarity
Remote IRR
Trigger Mode
Mask
Reserved
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
IOAPIC ID Register [Indirect Address Offset = 00H] RW
Bits Default
23:0 000000h
27:24 0h
31:28 0h
Bits Default
7:0 21h
14:8 00h
15 1b
23:16 17h
31:24 00h
Bits Default
23:0 000000h
27:24 0h
31:28 0h
Bits Default
7:0 00h
10:8 0h
11 0b
12 0b
13 0b
14 0b
15 0b
16 1b
31:17 0000h
55:32 000000h
Description
IOAPIC device ID for APIC serial bus delivery mode
Description
PCI 2.2 compliant
IRQ pin assertion supported
24 entries [23:0]
Description
Arbitration ID for APIC serial bus delivery mode
Description
Interrupt vector associated with this interrupt input
000 – Fixed
001 – Lowest Priority
010 – SMI/PMI
011 – <reserved>
100 – NMI
101 – INIT
110 – <Reserved>
111 – ExtINT
0 – Physical
1 – Logical
Read Only
0 – Idle
1 – Send Pending
0 – High
1 – Low
Read Only.
Used for level triggered interrupts only.
Set when interrupt message delivered.
Cleared by EOI special cycle transaction or write to
EOI register
0 – Edge
1 – Level
Mask the interrupt injection at the input of this device
Write 0 to unmask
Proprietary
IOXAPIC Registers
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