AMD SB600 Technical Reference Manual page 157

Field Name
PopUpReqHoldEn
(Applicable to ASIC
revision A21 and above)
TPRESET2 register
Field Name
T32_64
Reserved
SMI_Disable
Sel_wakeclk
Reserved
TESTENABLE register
Field Name
TFATAL_CLR
PWRBTTN_CLR
SHUTDOWN_CLR
Reserved
PWRBTTN_CLR register
Field Name
SoftPciRstEn
Gate_HpetIrq
UserResetEnable
PCIeNative
(Applicable to ASIC
revision A21 and above)
PCIeWakeMask
(Applicable to ASIC
revision A21 and above)
PCIeWakeNoSci
(Applicable to ASIC
revision A21 and above)
SoftPciRst
HideHpetBar
SoftPciRst register
Field Name
Reserved
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
TPRESET2 - RW – 8 bits - [PM_Reg: 52h]
Bits Default
7 0b Setting this bit to 1 will cause the pop-up request from the
NB, or from inside of the SB, to be captured and held until the
minimum LDTSTP# assertion time has expired.
TESTENABLE - RW – 8 bits - [PM_Reg: 53h]
Bits Default
0 0b Timing parameter used for C3 state in P4 system.
If set, the time from the reception of STOP_GNT# to SLP#
will be ~128 A-Link clocks. When it is cleared, the timing will
be ~64 A-Link clocks. Timing for CPU_STP#/PCI_STP# is
controlled similarly, except the value is 192 or 96 A-Link
clocks respectively when the bit is set or cleared.
2:1 00b
3 0b When set, SMI# generation will be disabled
4 0b Test feature: set 1 to use OSC as the wake up clock;
otherwise, use RTC CLK as the wake up clock
7:5 000b
PWRBTTN_CLR - RW – 8 bits - [PM_Reg: 54h]
Bits Default
0 0b Write 1 to clear the TFATAL status bit
1 0b Write 1 to clear the Power Button status bit
2 0b Write 1 to clear the SHUTDOWN#/GPIO5/SMARTVOLT2
status bit
7:3 0000_0b
SoftPciRst – RW – 8 bits – [PM_Reg:55h]
Bits Default
0 1b This bit enables both the soft PCIRST and the THRMTRIP
function.
1 0b Set to 1 to let HPET enable bit to control IRQ output
2 1b When set, GPM7 becomes user reset pin.
3 0b Setting this bit to 1 will cause PCIeHotPlug PCIePme and
WakeAsGevent status to not be set by corresponding events
as required by PCIe native mode.
4 0b Setting this bit will cause PCIEXP_WAKE_STS and
PCIEXP_WAKE_DIS to not be visible as required by WinXP.
5 0b Setting this bit will cause PCIEXP_WAKE_STS to not
generate SCI.
6 0b Setting bit 6 will cause a PCIRST.
7 0b Set to1 to make Bar1 in SM configuration space invisible (can
Not write and always read 0)
Reserved – 8 bits - [PM_Reg: 56h]
Bits Default
7:0 00h
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 157