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Field Name
Reserved
Timer1ExpEn
Timer2ExpEn
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
SOS3ToS5Enable2
SOS3ToS5Enable3
NoStatusControl0
NoStatusControl1
MiscEnable7C
DprSlpVrMinTime
SMAF0
SMAF1
SMAF2
SMAF3
WakePinCntl
CF9Rst
ThermThrotCntl
LdtStpCmd
LdtStartTime
AgpStartTime
LdtAgpTimeCntl
StutterTime
StpClkDlyTime
AbPmeCntl
FakeAsr
FakeAsrEn
GEVENTOUT
GEVENTEN
GEVENTIN
GPM98OUT
GPM98EN
GPM98IN
K8C1ePort
EnhanceControl
K8C1eReadPort
MsiSignature
AutoArbDisWaitTime
Programlo4RangeLo
Programlo4RangeHi
Programlo5RangeLo
Programlo5RangeHi
Programlo6RangeLo
Programlo6RangeHi
Programlo7RangeLo
Programlo7RangeHi
PIO7654Enable
PIO7654Status
PllDebug
AltDebugBusCntrl
C2Count
C3Count
MiscControl - RW – 8 bits - [PM_Reg: 00h]
Bits
Default
0
0b
1
0b
2
0b
Description
Set to 1 to enable SMI# when PM_TIMER1 expires. When
PM_TIMER1 (inactivity) expires, the SB will update bit 1 of
MiscStatus and issue SMI#. This bit allows the software to
disable/enable all inactivity timer reload enables at indexes
08,09, and 0A.
Set to 1 to enable SMI# when PM_TIMER2 expires.
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Offset Address
78h
79h
7Ah
7Bh
7Ch
7Dh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
94h
95h
96h
99:98h
9Ah
9Bh
9E:9Ch
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
B1:B0h
B2h
B3h
B4h
Page 141
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