AMD SB600 Technical Reference Manual page 222

Field Name
Slot Counter
Reserved
Bit Clock Counter
Reserved
Counter Register:
Field Name
Input Threshold
Reserved
Input FIFO Threshold Register: Input DMA's FIFOs threshold value.
Input DMA Link List Pointer - RW - 32 bits - [MEM_Reg: 20h]
Field Name
in DMA LL ptr en
in DMA LL Pointer
Input DMA Link List Pointer Register:
Field Name
in DMA DT start
Input DMA Discrete Table (DT) Start Pointer Register.
Field Name
in DMA DT next
Input DMA DT Next Pointer Register.
Field Name
in DMA DT current
Input DMA DT Current Pointer Register.
Input DMA DT Size & FIFO Info - R - 32 bits - [MEM_Reg: 30h]
Field Name
in DMA DT size
in FIFO Used
in FIFO Free
in DMA State
Reserved
Input DMA DT Size & FIFO info Register: Size of data associated with DT for input channels and number of FIFO
entries free and used for the input channels.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Counter - R - 32 bits - [MEM_Reg: 18h]
Bits Default
3:0 0h
7:4 0h
12:8 00h
31:13 00000h
Input FIFO Threshold - RW - 32 bits - [MEM_Reg: 1Ch]
Bits Default
4:0 00h
31:5 0000000h
Bits Default
0 0b
31:1 0000_0000h
Input DMA DT Start - R - 32 bits - [MEM_Reg: 24h]
Bits Default
31:0 0000_0000h
Input DMA DT Next - R - 32 bits - [MEM_Reg: 28h]
Bits Default
31:0 0000_0000h
Input DMA DT Current - R - 32 bits - [MEM_Reg: 2Ch]
Bits Default
31:0 0000_0000h
Bits Default
15:0 0000h
20:16 00h
25:21 06h
28:26 0h
31:20 000h
Description
The current slot number (0-12) which the AC97
controller handling.
For the tag slot, the value changes from 0 to F. For
other slots the value changes from 0 to 20.
Description
Threshold value for the Input Channel's FIFOs. (FIFO
size 16x20)
Description
Input DMA Link List Pointer enable
Pointer to the start of the Link List - to the first DT.
Description
Pointer to the start of data associated with current DT
for the input DMA
Description
Pointer to the next DT for the input DMA
Description
Pointer to the currently accessing memory address for
the input DMA
Description
Data size of DT for input DMA.
Number of filled FIFO entries of input DMA.
Number of free FIFO entries of input DMA.
Current state of the in DMA
AC '97 Controller Functional Descriptions
Proprietary Page 222