AMD SB600 Technical Reference Manual page 217

MSI Message Control Register- RW - 16 bits - [PCI_Reg: 42h]
Field Name
Multiple Message
Enable
64-bit Address
Capable
Reserved
MSI Message Address Register- RW – 32 bits - [PCI_Reg: 44h]
Field Name
Reserved
MSI Address
MSI Message Data Register- RW – 16 bits - [PCI_Reg: 48h]
Field Name
MSI Data
MSI Program Weight Register RW- 8 bits - [PCI_Reg: 4Ch]
Field Name
MSI Program Weight
Reserved
UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 50h]
Field Name
Reserved
Base1Enable
Reserved
LargeMemEnable
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
6:4 0b Software programs a 3-bit value into this field indicating the
actual number of messages allocated to the device. The number
allocated can be equal or less than the number actually
requested. The field is encoded as follows:
Value
000b
001b
010b
011b
100b
101b
110b
111b
7 0b Hardwired to 0 to indicates that function does not implement the
upper 32 bits of the Message Address register and is incapable
of generating a 64-bit memory address.
15:8 00h
Bits Default
1:0 Reserved.
31:2 0000_00 Lower 32 bits of the system specified message address always
00h DW aligned.
Bits Default
15:0 0h System-specified message.
Bits Default
5:0 000100 This register specifies the programmable priority of modem device's
b message signaled interrupt request.
7:6 0h
Bits Default
0 0b
1 0b When set, Base 1 (offset 14h) becomes writeable.
2 0b
3 0b When set, bits [13:8] of base 0 (offset 10h) becomes unwritable.
This is to cause OS to allocate wider memory map for ac97.
31:4 0000_0
00h
Description
Number of Messages Requested
1
2
4
8
16
32
Reserved
Reserved
Description
Description
Description
Description
AC '97 Controller Functional Descriptions
Proprietary Page 217