Gpoc; Table 4-2: Gpoc Pins - AMD SB600 Technical Reference Manual

Pin Name Multi-function
(Note 1) Selection
Notes:
1–In this table, the "GPIO" portion of the pin name has been put at the front of the names for the sake of clarity, making the pin names
different from how they appear in the AMD SB600 Databook.
2–Register A9h[7:0] is addressed as A8[15:8] in some AMD documents.
3–Register AAh[7:0] is addressed as A8[23:16] in some AMD documents.
4–Register BDh[7:0] is addressed as BCh[15:8] in some AMD documents.
5–Register 0A2h[15:0] is addressed as 0A0h[31:16] in some AMD documents.
4.1.2

GPOC

The two pairs of GPOC[3:2] and GPOC[1:0] pins are multi-purpose pins. They can be used as SMBus data
and clock pins or general purpose input/output pins. When used as output pins, they are open collectors and
need pull-up resistors for output high. Input/output programming is accomplished through the register pair
C50h/C51h in index/data mode.
GPOC[3:2] pins are in the S5 power plane. GPOC[1:0] pins are in the S0 power plane.
The index register 12h is used to access GPOC pins and is defined as follows:

Table 4-2: GPOC Pins

IO C50h/C51h
index 12h
Bit
0 GPOC0 Status
1 GPOC1 Status
2 GPOC0_OE
3 GPOC1_OE
4 GPOC2 Status
5 GPOC3 Status
6 GPOC2_OE
7 GPOC3_OE
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Output Enable
(On SMBus
Controller)
Bus 00h/ Dev14h/
Fun00
Field Name Default
Input if GPI
(On SMBus
Controller)
Bus 00h/
Dev14h/ Fun00
-- GPOC0 Input read status
-- GPOC1 Input read status
1 0 = GPOC0 is asserted low
1 = GPOC0 is tri-state
1 0 = GPOC1 is asserted low
1 = GPOC1 is tri-state
-- GPOC2 Input read status
-- GPOC3 Input read status
0: GPOC2 is asserted low
1
1: GPOC2 is tri-state
1 0: GPOC3 is asserted low
1: GPOC3 is tri-state
Proprietary
Output if GPO Power
(On SMBus Domain
Controller)
Bus 00h/
Dev14h/ Fun00
Description
GPIO/GPOC
Page 282