AMD K5 Manuals

AMD K5 Manuals

Manuals and User Guides for AMD K5. We have 1 AMD K5 manual available for free PDF download: Technical Reference Manual

AMD K5 Technical Reference Manual

AMD K5 Technical Reference Manual (406 pages)

Brand: AMD | Category: Computer Hardware | Size: 6.06 MB

Table of Contents

Table of Contents
3
1 Overview

21
- Features
  22
2 Internal Architecture

25
- Figure 2-1. Internal Architecture, with Pipeline Stage
  26
- Prefetch and Predecode
  27
- Execution Pipeline
  28
  - Figure 2-2. Pipeline Stage Functions
    29
  - Fetch
    30
  - Decode
    31
  - Execute
    32
    
    Integer/Shift Units
    33
    
    Table 2-1. ALU Instruction Classes
    33
    
    Branch Unit
    34
    
    Floating-Point Unit
    34
    
    Load/Store Units
    34
  - Result
    35
  - Retire
    36
  - Cache Organization and Management
    37
  - Instruction Cache
    38
  - Data Cache
    39
  - Cache Tags
    40
  - Cache-Line Fills
    41
  - Cache Coherency
    42
    
    Table 2-2. Cache States for Read and Write Accesses
    43
    
    Table 2-3. Cache States for Snoops, Invalidation, and Replacements
    44
    
    Inquire Cycles
    45
    
    Internal Snooping
    46
    
    Table 2-4. Snoop Action
    46
  - Snooping
    45
  - Buffers
    47
    
    Line-Fill Buffers
    47
    
    Prefetch Cache
    48
    
    Store Buffer
    48
    
    Replacement and Invalidation Writeback Buffer
    49
    
    Snoop Writeback Buffer
    50
    
    Memory Management Unit (MMU)
    50
  - Storage Model
    50
  - Read/Write Reordering
    51
  - Segmentation
    51
  - Paging and the Tlbs
    52
3 Software Environment and Extensions

55
4 Performance

91
- Code Optimization
  91
  - General Superscalar Techniques
    91
  - Techniques Specific to the AMD-K5 Processor
    93
- Dispatch and Execution Timing
  95
5 Bus Interface

117
- Figure 5-1. Signal Groups
  118
- Table 5-1. Summary of Signal Characteristics
  118
- Signal Overview
  118
- Signal Descriptions
  133
  - A20M (Address Bit 20 Mask)
    134
  - A31–A3 (Address Bus)
    136
  - Table 5-4. Address-Generation Sequence During Bursts
    137
  - ADS (Address Strobe)
    140
  - ADSC (Address Strobe Copy)
    143
  - AHOLD (Address Hold)
    144
  - AP (Address Parity)
    147
  - APCHK (Address Parity Check)
    148
  - BE7–BE0 (Byte Enables)
    149
  - Table 5-5. Relation of BE7-BE0 to Other Signals
    150
  - Table 5-6. Encodings for Special Bus Cycles
    151
  - Table 5-7. Processor-To-Bus Clock Ratios
    152
  - BOFF (Backoff)
    153
  - Table 5-8. Outputs Floated When BOFF Is Asserted
    154
  - BRDY (Burst Ready)
    157
  - BRDYC (Burst Ready)
    160
  - BREQ (Bus Request)
    161
  - BUSCHK (Bus Check)
    162
  - CACHE (Cacheable Access)
    165
  - Table 5-9. MESI-State Transitions for Reads
    167
  - CLK (Bus Clock)
    168
  - D/C (Data or Code)
    169
  - D63–D0 (Data Bus)
    171
  - Table 5-10. Relation between D63-D0, BE7-BE0, and DP7-DP0
    172
  - DP7–DP0 (Data Parity)
    173
  - EADS (External Address Strobe)
    174
  - EWBE (External Write Buffer Empty)
    178
  - FERR (Floating-Point Error)
    180
  - FLUSH (Cache Flush)
    181
  - FRCMC (Functional-Redundancy Check Master/Checker)
    184
  - HIT (Inquire-Cycle Hit)
    186
  - Table 5-11. MESI-State Transitions for Inquire Cycles
    187
  - HITM (Inquire Cycle Hit to Modified Line)
    188
  - Table 5-12. Outputs Floated When HLDA Is Asserted
    190
  - HLDA (Bus-Hold Acknowledge)
    190
  - HOLD (Bus-Hold Request)
    192
  - IERR (Internal Error)
    194
  - IGNNE (Ignore Numeric Error)
    195
  - INIT (Initialization)
    197
  - INTR (Maskable Interrupt)
    200
  - Table 5-13. Interrupt Acknowledge Operation Definition
    201
  - INV (Invalidate Cache Line)
    204
  - KEN (External Cache Enable)
    205
  - LOCK (Bus Lock)
    207
  - M/IO (Memory or I/O)
    211
  - NA (Next Address)
    212
  - NMI (Non-Maskable Interrupt)
    213
  - PCD (Page Cache Disable)
    215
  - PCHK (Parity Status)
    217
  - PEN (Parity Enable)
    218
  - PRDY (Probe Ready)
    219
  - Table 5-14. PWT, Writeback/Writethrough, and MESI
    221
  - PWT (Page Writethrough)
    221
  - R/S (Run or Stop)
    223
  - RESET (Reset)
    225
  - Table 5-15. Register State after RESET or INIT
    226
  - Table 5-16. Outputs at RESET
    228
  - SCYC (Split Cycle)
    230
  - SMI (System Management Interrupt)
    232
  - SMIACT (System Management Interrupt Active)
    237
  - STPCLK (Stop Clock)
    238
  - TCK (Test Clock)
    243
  - TDI (Test Data Input)
    244
  - TDO (Test Data Output)
    245
  - TMS (Test Mode Select)
    246
  - TRST (Test Reset)
    247
  - W/R (Write or Read)
    248
  - WB/WT (Writeback or Writethrough)
    249
  - Table 5-17. MESI-State Transitions for Reads
    250
  - Table 5-18. MESI-State Transitions for Writes
    251
- Bus Cycle Overview
  252
  - Table 5-19. Bus Cycle Definitions
    252
  - Addressing
    253
  - Alignment
    253
  - Bus Speed and Typical DRAM Timing
    255
  - Bus-Cycle Priorities
    255
- Bus Cycle Timing
  256
6 System Design

313
- Memory
  313
- Cache
  320
  - L2 Cache
    321
  - Cacheability and Cache-State Control
    321
  - Writethrough Vs. Writeback Coherency States
    322
  - Inquire Cycles
    324
  - Bus Arbitration for Inquire Cycles
    326
    
    BOFF Arbitration
    327
    
    Figure 6-3. BOFF Example
    328
    
    AHOLD Arbitration
    329
    
    Figure 6-4. AHOLD and BOFF Example
    330
    
    HOLD Arbitration
    331
  - Write-Once Protocol
    331
  - Figure 6-5. Write-Once Protocol
    333
  - Cache Invalidations
    334
  - A20M Masking of Cache Accesses
    334
- System Management Mode (SMM)
  335
  - Operating Mode and Default Register Values
    336
  - Table 6-1. Initial State of Registers in SMM
    337
  - SMM State-Save Area
    337
  - Table 6-2. SMM State-Save Area Map
    338
  - SMM Revision Identifier
    340
  - SMM Base Address
    340
  - Halt Restart Slot
    342
  - I/O Trap Dword
    343
  - I/O Trap Restart Slot
    343
  - Exceptions and Interrupts in SMM
    344
  - SMM Compatibility with Pentium Processor
    345
- Clock Control
  345
  - State Transitions
    346
  - Halt State
    346
  - Figure 6-6. Clock Control State Transitions
    348
  - Stop Grant State
    349
  - Stop Grant Inquire State
    349
  - Stop Clock State
    350
  - Clock Control Compatibility with Pentium Processor
    350
- Power and Ground Design
  350
- Figure 6-7. V
  352
- Power-Up Requirements
  352
- Noise Reduction
  353
- Thermal Design
  354
- Design Support and Peripheral Products
  355
7 Test and Debug

357
- Hardware Configuration Register (HWCR)
  359
- Table 7-1. Hardware Configuration Register (HWCR) Fields
  360
- Built-In Self Test (BIST)
  361
  - Normal bist
    361
  - Table 7-2. bist Error Bit Definition in EAX Register
    362
  - Test Access Port (TAP) bist
    362
- Output-Float Test
  363
- Debug Registers
  372
  - Standard Debug Functions
    372
  - I/O Breakpoint Extension
    372
  - Debug Compatibility with Pentium Processor
    373
- Branch Tracing
  373
- Table 7-4. Branch-Trace Message Special Bus Cycle Fields
  374
- Functional-Redundancy Checking
  374
- Boundary-Scan Test Access Port (TAP)
  375
- Hardware Debug Tool (HDT)
  379
A.1 Bus Signals

382
- A.1.1 Signal Comparison
  382
Appendix A Compatibility with the Pentium and 486 Processors

382
A.2 Bus Interface

385
A.3 Bus Mastering Operations (Including Snooping)

388
A.4 Memory Management

391
- A.4.1 Speculative TLB Refills
  391
  - Type of Instruction
    391
A.5 Power Saving Features

392
- A.5.1 STPCLK in Halt State
  392
  - One Instruction Executes
    392
- A.5.3 Simultaneous I/O SMI Trap and Debug Breakpoint Trap
  392
- A.5.4 SMM Save Area
  393
- A.5.5 NMI Recognition During SMM
  393
  - Comment
    393
A.6 Exceptions

394
- A.6.1 Limit Faults on an Invalid Instruction
  394
- A.6.2 Task Switch
  394
A.7 Debug

395

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