Ioxapic Registers; Direct Access Registers - AMD SB600 Technical Reference Manual

4.5

IOXAPIC Registers

Note: Some IOXAPIC functions are controlled by, and associated with, certain PCI configuration registers in
the SMBus/ACPI device. For more information refer to
0). The diagram below lists these IOXAPIC functions and the associated registers.
20, Function
4.5.1

Direct Access Registers

Note: The XAPIC_BASE_REGISTER has a power-on default value of FEC0_0000H.
IO Register Select Register RW [XAPIC_BASE_REGISTER + 00H]
Field Name
Indirect Address Offset
Reserved
Used to determine which register is manipulated during an IO Window Register read/write operation.
IO Window Register RW [XAPIC_BASE_REGISTER + 10H]
Field Name
Mapped by the value in the IO Register Select Register, to the designated indirect access register.
Technically a R/W register; however, the read/write capability is determined by the indirect access register
referenced by the IO Register Select Register.
IRQ Pin Assertion Register RW [XAPIC_BASE_REGISTER + 20H]
Field Name
Input IRQ
<reserved>
Write to this register will trigger an interrupt associated with the redirection table entry referenced by the IRQ
number. Currently the redirection table has 24 entries. Write with IRQ number greater than 17H has no effect.
Field Name
Vector
<reserved>
Write to this register will clear the remote IRR bit in the redirection table entry found matching the interrupt vector.
This provides an alternate mechanism other than PCI special cycle for EOI to reach IOXAPIC.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
7:0 00h
31:8
Bits Default
Bits Default
7:0 00h
31:8 0000000h
EOI Register W [XAPIC_BASE_REGISTER + 40H]
Bits Default
7:0 00h
31:8 0000000h
section 2.3: SMBus Module and ACPI Block (Device
Description
Indirect Address Offset to IO Window Register
Description
Description
IRQ number for the requested interrupt
Description
Interrupt vector
Proprietary
IOXAPIC Registers
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