AMD SB600 Technical Reference Manual page 163

Field Name
WatchDogTimerBase2
WatchDogTimerBase2 register
Field Name
WatchDogTimerBase3
WatchDogTimerBase3 register
Field Name
S_LdtStartTime
S_LdtStartTime register
Field Name
Reserved
P4C34PopUpEn
C2EnhanceEn
Reserved
VidFidExtraDelayEn
VidFidExtraDelaySelect
EnhanceOption register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
WatchDogTimerBase2 – RW – 8 bits – [PM_Reg:6Eh]
Bits Default
7:0 00h
WatchDogTimerBase3 – RW – 8 bits – [PM_Reg:6Fh]
Bits Default
7:0 00h
S_LdtStartTime – RW – 8 bits – [PM_Reg:70h]
Bits Default
7:0 00h
EnhanceOption – RW – 8 bits – [PM_Reg:71h]
Bits Default
0 0b
1 0b
2 0b
3 0b
4 0b
7:5 000b
Description
WatchDogTimer Base address [23:16]
Description
WatchDogTimer Base address [31:24]
Description
This register defines the delay between SUS_STAT# assertion
and LDTSTP# assertion when the K8 system enters ACPI S
states, in 1us increment, with 1us uncertainty.
Description
If enabled, for P4 system C3/4 can pop up to C2 for internal
DMA request and back down to C3/4 after A-link bus is idle for
number of clocks defined by PopUpEndTime.
1 = Enable
0 = Disable
For both P4 and K8 system, in C2 state NB can toggle
SLP#/LDTSTP#. When entering C2 state, SB sends out
STPCLK# assertion message. NB takes control of
SLP#/LDTSTP#. When exiting C2 state, SB sends out
STPCLK# de-assertion message. NB de-assert
SLP#/LDTSTP# if needed. If this bit is enabled, SB will wait for
NB to send the same message back then de-assert STPCLK#
signal for P4 system or send another STPCLK# de-assertion
message for K8 system. If this bit is disabled, SB will not wait
for NB to send the message back.
1 = Enable
0 = Disable
If enabled, extra duration of LDTSTP# assertion as specified
by VidFidExtraDelaySelect will be added to the VID/FID
change sequence.
1 = Enable
0 = Disable
3'b000: 0ns
3'b001: 140ns
3'b010: 210ns
3'b011: 280ns
3'b110: 350ns
3'b111: 420ns
3'b100: 490ns
3'b101: 560ns
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 163