AMD SB600 Technical Reference Manual page 148

Field Name
MouseKbMonitorStatus
ProgramIo3Status
ProgramIo2Status
ProgramIo1Status
ProgramIo0Status
IOMonitorStatus register
InactiveTmrEventEnable4 - RW – 8 bits - [PM_Reg: 1Eh]
Field Name
AD_LIB_Timer1Enable
MIDI_Timer1Enable
Audio_Timer1Enable
Keyboard_Time1Enable
PIO3_Timer1Enable
PIO2_Timer1Enable
PIO1_Timer1Enable
PIO0_Timer1Enable
InactiveTmrEventEnable4 register.
Field Name
Reserved
AcpiPm1EvtBlkLo
AcpiPm1EvtBlkLo register.
Field Name
AcpiPm1EvtBlkHi
AcpiPm1EvtBlkHi register.
Field Name
Reserved
AcpiPm1CntBlkLo
AcpiPm1CntBlkLo register.
Field Name
AcpiPm1CntBlkHi
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh]
Bits Default
3 - Mouse/keyboard status bit; write 1'b1 to clear the status bit
4 - Programmable IO 3 status bit; write 1'b1 to clear the status
bit
5 - Programmable IO 2 status bit; write 1'b1 to clear the status
bit
6 - Programmable IO 1 status bit; write 1'b1 to clear the status
bit
7 - Programmable IO 0 status bit; write 1'b1 to clear the status
bit
Bits Default
0 0b Enables Timer1 reload on AD_LIB inactivity
1 0b Enables Timer1 reload on MIDI inactivity
2 0b Enables Timer1 reload on Audio inactivity
3 0b Enables Timer1 reload on Keyboard/Mouse port inactivity
4 0b Enables Timer1 reload on PIO3 port inactivity
5 0b Enables Timer1 reload on PIO2 port inactivity
6 0b Enables Timer1 reload on PIO1 port inactivity
7 0b Enables Timer1 reload on PIO0 port inactivity
AcpiPm1EvtBlkLo - RW – 8 bits - [PM_Reg: 20h]
Bits Default
1:0 00b
7:2 00h These bits define the least significant byte of the 16 bit I/O
range base address of the ACPI power management Event
Block. Bit 2 corresponds to Addr[2] and bit 7 corresponds to
Addr[7].
AcpiPm1EvtBlkHi - RW – 8 bits - [PM_Reg: 21h]
Bits Default
7:0 00h These bits define the most significant byte of the 16 bit I/O
range base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPm1CntBlkLo - RW – 8 bits - [PM_Reg: 22h]
Bits Default
0 0b
7:1 00h These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management Control block.
Bit 1 corresponds to Addr[1] and bit 7 corresponds to Addr[7].
AcpiPm1CntBlkHi - RW – 8 bits - [PM_Reg: 23h]
Bits Default
7:0 00h These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
Description
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 148