AMD SB600 Technical Reference Manual page 225

Output DMA 1/2/3 FIFO Info– R - 32 bits - [MEM_Reg: 70h]
Field Name
out DMA3 Used
Reserved
out DMA1 Free
out DMA2 Free
out DMA3 Free
Reserved
Output DMA1/2/3 FIFO Used/Free Register:
Field Name
Gpio Out Data en
Gpio Out Data
Reserved
Gpio Out Data Register: Data to the modem.
Field Name
Input Gpio data
Input Gpio Codec ID
Reserved
Input Gpio data Register: Data from the modem.
Field Name
Modem mirror
Modem mirror Register.
Field Name
Audio mirror
Audio mirror Register.
Field Name
Output DMA1 Fifo Flush
Output DMA2 Fifo Flush
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
14:10 00h
15 0b
20:16 00h
25:21 00h
30:26 00h
31 0b
GPIO Out Data– RW - 32 bits - [MEM_Reg: 74h]
Bits Default
0 0b
20:1 000h
31:21 000h
Input GPIO Data– R - 32 bits - [MEM_Reg: 78h]
Bits Default
19:0 00000h
22:20 0h
31:23 00h
Modem Mirror– RW - 32 bits - [MEM_Reg: 7Ch]
Bits Default
31:0 0000_0000h
Audio Mirror– R - 32 bits - [MEM_Reg: 80h]
Bits Default
31:0 0000_0000h
Modem Fifo Flush– W - 32 bits - [MEM_Reg: 88h]
Bits Default
0 0b
1 0b
Description
Number of filled FIFO entries of Output DMA3 (FIFO
size 6).
Number of free FIFO entries of Output DMA1 (FIFO
size 6).
Number of free FIFO entries of Output DMA2 (FIFO
size 6).
Number of free FIFO entries of Output DMA3 (FIFO
size 6).
Description
Enables the sending of GPIO data on the next frame's
slot 12. Data comes from bit[20:1] of this register. This
bit has higher priority than reg0x08[22]. That means if
both this bit and reg0x08[22] are set, then GPIO data
comes from bit[20:1] of this register, not from DMA3.
Writing 1 to this bit enables this data to be sent out.
After some time, when data is sent out, this bit
automatically goes back to 0. Bit[20:1] can be written
only when this bit is 0.
Gpio Out Data
Description
Input Gpio(modem) data from AC'97 Codecs (ORed)
ID of Codec who send the Gpio data (001 - Master,
010- Slave1, 100 - Slave2)
Description
Data written by modem for communication with Audio.
Description
Data written by audio for communication with modem.
Description
Writing to this bit flushes modem output DMA1 fifo,
i.e., the indexes and Used/Free counts are reset.
Reading this bit returns 0.
Writing to this bit flushes modem output DMA2 fifo,
i.e., the indexes and Used/Free counts are reset.
Reading this bit returns 0.
AC '97 Controller Functional Descriptions
Proprietary Page 225