Table 4-2: Debug Straps - AMD SP5100 Data Book

AMD SP5100 Databook
Pad Name Strap Name
IMC_ENABLE
LPCCLK0
PCI_ROM_BOOT
PCIE_PLL_ENAB
LPCCLK1
LE
IMC_ENABLE
AZ_RST#
PCI_ROM_BOOT
PCICLK5 Reserved
PCICLK4 Reserved
PCICLK3 Debug_Straps
PCICLK2 Watchdog_Enable

Table 4-2: Debug Straps

Pad Name Strap Name
PCI_AD30 Reserved
PCI_AD29 Reserved
PCI_AD28 Reset_Length
22
Type Description
Integrated Microcontroller (IMC)
I 0 V – Disable IMC
3.3 V – Enable IMC
Revision A11 strap defination
Booting from PCI memory
0 V – disable PCI ROM boot (Default)
3.3 V – enable PCI ROM boot
II
Note: This feature is for debug pupose only. After a G3 →
S5 transition the system will allow boot from PCI memory
only once. Subsequent S5 → S0 transition will not boot
from PCI memory.
Enable PCI Expresse
0 V – Normal operation. PCI Express clock enabled for
internal PLL reference clock.
II
3.3 V – Test / debug. PCI Express clock disconnected
from internal PLL.
Revision A11 strap defination
Integrated Microcontroller (IMC)
I
0 V – disable IMC
3.3 V – enable IMC
Booting from PCI memory
0 V – disable PCI ROM boot (Default)
3.3 V – enable PCI ROM boot
Note: This feature is for debug pupose only. After a G3 →
II
S5 transition the system will allow boot from PCI memory
only once. Subsequent S5 → S0 transition will not boot
from PCI memory.
— Reserved
— Reserved
Enable/Disable additional straps for debugging (see
Table 4-2
)
II
0 V – use hardcoded defaults for Debug
Straps (Default)
3.3 V – enable additional Debug Straps
Watchdog function
II 0 V – disable watchdog function on NB_PWRGD ball
3.3 V – enable watchdog function on NB_PWRGD ball
Type Description
— Reserved (Internal PU of 15 kΩ)
— Reserved (Internal PU of 15 kΩ)
Generate a short reset
0 V – Use short reset (reserved, do not use)
II
3.3 V – Use long reset (Default)
(Internal PU of 15 kΩ)
SP5100 Strap Information
44409 Rev. 1.70 October 10
®
PLL