AMD SB600 Technical Reference Manual page 261

Field Name
SPI_OpCode
TxByteCount
RxByteCount
ExecuteOpCode
Reserved
SpiArbEnable
FifoPtrClr
FifoPtrInc
SpiAccessMacRomEn
SpiHostAccessRomEn
ArbWaitCount
SpiBridgeDisable
Reserved
SPI_RestrictedCmd1 Register- RW - 32 bits - [Mem_Reg 04h]
Field Name
RestrictedCmd0
RestrictedCmd1
RestrictedCmd2
RestrictedCmd3
SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h]
Field Name
RestrictedCmd4
RestrictedCmdWoAddr
0
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
SPI_FakeID
SPI_Cntrl0 Register- RW - 32 bits - [Mem_Reg 00h]
Bits Default
7:0 00h When software uses the alternate program method to
communicate with the SPI ROM, this register contains the
OPCODE
11:8 0h Number of bytes to be sent to SPI ROM
15:12 0h Number of bytes to be received from the SPI ROM
16 0b Write 1 to execute the transaction in the alternate program
registers. Write 0 has no effect. When the transaction is
complete, this bit will return 0. If the command is an illegal
command, the bit cannot be set and thereby cannot execute
18:17 00b
19 1b If a MAC is sharing the ROM with the SB, both chips will need
to go through an arbitration process before either one can
access the ROM. This bit enables the arbitration. If MAC is not
sharing the SPI ROM, BIOS should set this bit to 0 to speed up
the SPI ROM access
20 0b (write only) A write of 1 to this bit will clear the internal FIFO
pointer
21 0b (write only ) A write of 1 to this bit will cause the internal FIFO
pointer to be incremented by 1
22 1b This is a clear-once protection bit; once set, software cannot
access MAC's portion of the ROM space (lower 512KB).
23 1b This is a clear-once protection bit; once set, MAC cannot
access BIOS ROM space (upper 512KB)
26:24 100b Under ROM sharing mode (with the MAC) this defines the
amount of wait time this controller will assert HOLD# before it
should access the SPI ROM. This time is to allow the MAC to
sample HOLD#.
27 0b Setting this bit will disable the SPI bridge mode (SB600 will act
as a SPI-LPC bridge to the MAC)
31:28 0h
Bits Default
7:0 00h This defines a restricted command issued by the MAC which
will be checked by the SB600. If the opcode issued by the
MAC matches with this register and the address space is in the
BIOS space, this controller will simply ignore the command for
the case of bridge mode. For peer mode, the SPI controller will
jam the entire interface as an attempt to stop that transaction.
Note either SpiAccessMacRomEn and/or
SpiHostAccessRomEn bit is cleared, these registers become
read only and cannot be changed any more.
15:8 00h Same as RestrictedCmd0
23:16 00h Same as RestrictedCmd0
31:24 00h Same as RestrictedCmd0
Bits Default
7:0 00h Same as RestrictedCmd0
15:8 00h Same as RestrictedCmd0 except this command does not have
address
Description
Description
Description
LPC ISA Bridge (Device 20, Function 3)
Proprietary
Offset Address
1Ch
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