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Manuals and User Guides for AMD Geode SC3200. We have
1
AMD Geode SC3200 manual available for free PDF download: Data Book
AMD Geode SC3200 Data Book (428 pages)
Processor
Brand:
AMD
| Category:
Computer Hardware
| Size: 3.41 MB
Table of Contents
Table of Contents
3
List of Figures
5
List of Tables
9
1 0Overview
13
General Description
13
Figure 1-1. Block Diagram
13
Features
14
2 0Architecture Overview
17
GX1 Module
17
Table 2-1. SC3200 Memory Controller Register Summary
18
Table 2-2. SC3200 Memory Controller Registers
18
Video Processor Module
22
Core Logic Module
22
Super I/O Module
23
Clock, Timers, and Reset Logic
23
3 0Signal Definitions
25
Figure 3-1. Signal Groups
25
Ball Assignments
27
Table 3-1. Signal Definitions Legend
27
Figure 3-2. BGU481 Ball Assignment Diagram
28
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
29
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name
40
Strap Options
44
Table 3-4. Strap Options
44
Multiplexing Configuration
45
Table 3-5. Two-Signal/Group Multiplexing
45
Table 3-6. Three-Signal/Group Multiplexing
46
Table 3-7. Four-Signal/Group Multiplexing
48
Signal Descriptions
49
4 0General Configuration Block
69
Configuration Block Addresses
69
Table 4-1. General Configuration Block Register Summary
69
Multiplexing, Interrupt Selection, and Base Address Registers
70
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers
70
Watchdog
77
Figure 4-1. WATCHDOG Block Diagram
77
Table 4-3. WATCHDOG Registers
78
High-Resolution Timer
79
Table 4-4. High-Resolution Timer Registers
80
Clock Generators and Plls
81
Figure 4-2. Clock Generation Block Diagram
81
Figure 4-3. Recommended Oscillator External Circuitry
82
Table 4-5. Crystal Oscillator Circuit Components
82
Table 4-6. Core Clock Frequency
83
Table 4-7. Strapped Core Clock Frequency
83
Table 4-8. Clock Generator Configuration
85
5 0Superi/O Module
87
Figure 5-1. SIO Block Diagram
87
Features
88
Module Architecture
89
Figure 5-2. Detailed SIO Block Diagram
89
Configuration Structure / Access
90
Figure 5-3. Structure of the Standard Configuration Register File
90
Table 5-1. SIO Configuration Options
90
Table 5-2. LDN Assignments
90
Standard Configuration Registers
92
Figure 5-4. Standard Configuration Registers Map
92
Table 5-3. Standard Configuration Registers
93
Table 5-4. SIO Control and Configuration Register Map
95
Table 5-5. SIO Control and Configuration Registers
95
Table 5-6. Relevant RTC Configuration Registers
96
Table 5-7. RTC Configuration Registers
97
Table 5-8. Relevant SWC Registers
98
Table 5-9. Relevant IRCP/SP3 Registers
99
Table 5-10. IRCP/SP3 Configuration Register
99
Table 5-11. Relevant Serial Ports 1 and 2 Registers
100
Table 5-12. Serial Ports 1 and 2 Configuration Register
100
Table 5-13. Relevant ACB1 and ACB2 Registers
101
Table 5-14. ACB1 and ACB2 Configuration Register
101
Table 5-15. Relevant Parallel Port Registers
102
Table 5-16. Parallel Port Configuration Register
102
Real-Time Clock (RTC)
103
Figure 5-5. Recommended Oscillator External Circuitry
103
Table 5-17. Crystal Oscillator Circuit Components
103
Figure 5-6. External Oscillator Connections
104
Figure 5-7. Divider Chain Control
104
Figure 5-8. Power Supply Connections
106
Figure 5-9. Typical Battery Configuration
106
Figure 5-10. Typical Battery Current: Battery Backed Power Mode @ T C = 25°C
106
Figure 5-11. Typical Battery Current: Normal Operation Mode
106
Table 5-18. System Power States
107
Figure 5-12. Interrupt/Status Timing
108
Table 5-19. RTC Register Map
109
Table 5-20. RTC Registers
109
Table 5-21. Divider Chain Control / Test Selection
112
Table 5-22. Periodic Interrupt Rate Encoding
112
Table 5-23. BCD and Binary Formats
112
Table 5-24. Standard RAM Map
113
Table 5-25. Extended RAM Map
113
System Wakeup Control (SWC)
114
Table 5-26. Time Range Limits for CEIR Protocols
114
Table 5-27. Banks 0 and 1 - Common Control and Status Register Map
115
Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
115
Table 5-29. Banks 0 and 1 - Common Control and Status Registers
116
Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
117
Access.bus Interface
119
Figure 5-13. Bit Transfer
119
Figure 5-14. Start and Stop Conditions
119
Figure 5-15. Access.bus Data Transaction
120
Figure 5-16. Access.bus Acknowledge Cycle
120
Figure 5-17. a Complete Access.bus Data Transaction
121
Table 5-31. ACB Register Map
124
Table 5-32. ACB Registers
124
Legacy Functional Blocks
127
Table 5-33. Parallel Port Register Map for First Level Offset
127
Table 5-34. Parallel Port Register Map for Second Level Offset
127
Table 5-35. Parallel Port Bit Map for First Level Offset
128
Table 5-36. Parallel Port Bit Map for Second Level Offset
128
Figure 5-18. UART Mode Register Bank Architecture
129
Table 5-37. Bank 0 Register Map
129
Table 5-38. Bank Selection Encoding
130
Table 5-39. Bank 1 Register Map
130
Table 5-40. Bank 2 Register Map
130
Table 5-41. Bank 3 Register Map
130
Table 5-42. Bank 0 Bit Map
131
Table 5-43. Bank 1 Bit Map
131
Table 5-44. Bank 2 Bit Map
132
Table 5-45. Bank 3 Bit Map
132
Figure 5-19. IRCP/SP3 Register Bank Architecture
133
Table 5-46. Bank 0 Register Map
133
Table 5-47. Bank Selection Encoding
134
Table 5-48. Bank 1 Register Map
134
Table 5-49. Bank 2 Register Map
134
Table 5-50. Bank 3 Register Map
135
Table 5-51. Bank 4 Register Map
135
Table 5-52. Bank 5 Register Map
135
Table 5-53. Bank 6 Register Map
136
Table 5-54. Bank 7 Register Map
136
Table 5-55. Bank 0 Bit Map
136
Table 5-56. Bank 1 Bit Map
137
Table 5-57. Bank 2 Bit Map
137
Table 5-58. Bank 3 Bit Map
137
Table 5-59. Bank 4 Bit Map
137
Table 5-60. Bank 5 Bit Map
138
Table 5-61. Bank 6 Bit Map
138
Table 5-62. Bank 7 Bit Map
138
6 0Core Logic Module
139
Feature List
139
Module Architecture
140
Figure 6-1. Core Logic Module Block Diagram
140
Table 6-1. Physical Region Descriptor Format
143
Table 6-2. Ultradma/33 Signal Definitions
144
Figure 6-2. Non-Posted Fast-PCI to ISA Access
146
Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled
147
Figure 6-4. ISA DMA Read from PCI Memory
148
Figure 6-5. ISA DMA Write to PCI Memory
148
Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
149
Figure 6-6. PCI Change to Sub-ISA and Back
150
Figure 6-7. PIT Timer
152
Figure 6-8. PIC Interrupt Controllers
153
Table 6-4. PIC Interrupt Mapping
153
Figure 6-9. PCI and IRQ Interrupt Mapping
154
Figure 6-10. SMI Generation for NMI
155
Table 6-5. Wakeup Events Capability
157
Table 6-6. Power Planes Control Signals Vs. Sleep States
158
Table 6-7. Power Planes Vs. Sleep/Global States
158
Table 6-8. Power Management Events
158
Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
163
Table 6-9. Device Power Management Programming Summary
164
Table 6-10. Bus Masters that Drive Specific Slots of the AC97 Interface
165
Table 6-11. Physical Region Descriptor Format
166
Figure 6-12. PRD Table Example
167
Figure 6-13. AC97 V2.0 Codec Signal Connections
168
Figure 6-14. Audio SMI Tree Example
170
Figure 6-15. Typical Setup
171
Table 6-12. Cycle Types
172
Table 6-44. DMA
172
Register Descriptions
173
Table 6-13. PCI Configuration Address Register (0Cf8H)
173
Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary
174
Table 6-15. F0BAR0: GPIO Support Registers Summary
177
Table 6-16. F0BAR1: LPC Support Registers Summary
177
Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
178
Table 6-18. F1BAR0: SMI Status Registers Summary
178
Table 6-19. F1BAR1: ACPI Support Registers Summary
179
Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
180
Table 6-21. F2BAR4: IDE Controller Support Registers Summary
181
Table 6-22. F3: PCI Header Registers for Audio Support Summary
181
Table 6-23. F3BAR0: Audio Support Registers Summary
182
Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
183
Table 6-25. F5BAR0: I/O Control Support Registers Summary
183
Table 6-26. PCIUSB: USB PCI Configuration Register Summary
184
Table 6-27. USB_BAR: USB Controller Registers Summary
185
Table 6-28. ISA Legacy I/O Register Summary
186
Chipset Register Space
188
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support
188
Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers
222
Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
226
Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support
234
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers
235
Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers
245
Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
255
Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
259
Table 6-37. F3: PCI Header Registers for Audio Configuration
261
Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers
262
Table 6-39. F5: PCI Header Registers for X-Bus Expansion
276
Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
280
Table 6-41. PCIUSB: USB PCI Configuration Registers
282
Table 6-42. Usb_Bar+Memory Offset: USB Controller Registers
285
Table 6-43. DMA Channel Control Registers
295
Table 6-45. Programmable Interval Timer Registers
301
Table 6-46. Programmable Interrupt Controller Registers
303
Table 6-47. Keyboard Controller Registers
306
Table 6-48. Real-Time Clock Registers
307
Table 6-49. Miscellaneous Registers
307
7 0Video Processor Module
309
Module Architecture
310
Figure 7-1. Video Processor Block Diagram
310
Functional Description
311
Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
312
Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
312
Figure 7-4. VIP Block Diagram
313
Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer
315
Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
316
Figure 7-7. Video Block Diagram
317
Figure 7-8. Horizontal Downscaler Block Diagram
318
Figure 7-9. Linear Interpolation Calculation
319
Figure 7-10. Mixer/Blender Block Diagram
320
Table 7-1. Valid Mixing/Blending Configurations
321
Figure 7-11. Graphics/Video Frame with Alpha Windows
322
Table 7-2. Truth Table for Alpha Blending
323
Figure 7-12. Color Key and Alpha Blending Logic
324
Figure 7-13. TFT Power Sequence
325
Figure 7-14. PLL Block Diagram
326
Register Descriptions
327
Table 7-3. F4: PCI Header Registers for Video Processor Support Summary
327
Table 7-4. F4BAR0: Video Processor Configuration Registers Summary
327
Table 7-5. F4BAR2: VIP Support Registers Summary
329
Table 7-6. F4: PCI Header Registers for Video Processor Support Registers
330
Table 7-7. F4Bar0+Memory Offset: Video Processor Configuration Registers
332
Table 7-8. F4Bar2+Memory Offset: VIP Configuration Registers
345
8 0Debugging and Monitoring
349
Testability (JTAG)
349
Table 8-1. JTAG Mode Instruction Support
349
9 0Electrical Specifications
351
General Specifications
351
Table 9-1. Electro Static Discharge (ESD)
351
Table 9-2. Absolute Maximum Ratings
351
Table 9-3. Operating Conditions
352
Table 9-4. Power Planes of External Interface Signals
353
Table 9-5. System Conditions Used to Measure SC3200 Current During on State
354
Table 9-6. DC Characteristics for on State
354
Table 9-7. DC Characteristics for Active Idle, Sleep, and off States
355
Table 9-8. Ball Capacitance and Inductance
355
Table 9-9. Balls with PU/PD Resistors
356
DC Characteristics
357
Table 9-10. Buffer Types
357
Figure 9-1. Differential Input Sensitivity for Common Mode Range
360
AC Characteristics
362
Figure 9-2. Drive Level and Measurement Points
362
Table 9-11. Default Levels for Measurement of Switching Parameters
362
Figure 9-3. Memory Controller Drive Level and Measurement Points
363
Table 9-12. Memory Controller Timing Parameters
364
Figure 9-4. Memory Controller Output Valid Timing Diagram
365
Figure 9-5. Read Data in Setup and Hold Timing Diagram
365
Figure 9-6. Video Input Port Timing Diagram
366
Table 9-13. Video Input Port Timing Parameters
366
Figure 9-7. TFT Timing Diagram
367
Table 9-14. TFT Timing Parameters
367
Table 9-15. Access.bus Input Timing Parameters
368
Table 9-16. Access.bus Output Timing Parameters
368
Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram
369
Figure 9-9. ACB Start and Stop Condition Timing Diagram
369
Figure 9-10. ACB Start Condition Timing Diagram
370
Figure 9-11. ACB Data Bit Timing Diagram
370
Figure 9-12. Testing Setup for Slew Rate and Minimum Timing
371
Table 9-17. PCI AC Specifications
371
Figure 9-13. V/I Curves for PCI Output Signals
372
Figure 9-14. PCICLK Timing and Measurement Points
373
Table 9-18. PCI Clock Parameters
373
Figure 9-15. Load Circuits for Maximum Time Measurements
374
Table 9-19. PCI Timing Parameters
374
Figure 9-16. Output Timing Measurement Conditions
375
Table 9-20. Measurement Condition Parameters
375
Figure 9-17. Input Timing Measurement Conditions
376
Figure 9-18. PCI Reset Timing
376
Table 9-21. Sub-ISA Timing Parameters
377
Figure 9-19. Sub-ISA Read Operation Timing Diagram
379
Figure 9-20. Sub-ISA Write Operation Timing Diagram
380
Figure 9-21. LPC Output Timing Diagram
381
Figure 9-22. LPC Input Timing Diagram
381
Table 9-22. LPC and SERIRQ Timing Parameters
381
Figure 9-23. IDE Reset Timing Diagram
382
Table 9-23. IDE General Timing Parameters
382
Table 9-24. IDE Register Transfer To/From Device Timing Parameters
383
Figure 9-24. Register Transfer To/From Device Timing Diagram
384
Table 9-25. IDE PIO Data Transfer To/From Device Timing Parameters
385
Figure 9-25. PIO Data Transfer To/From Device Timing Diagram
386
Table 9-26. IDE Multiword DMA Data Transfer Timing Parameters
387
Figure 9-26. Multiword DMA Data Transfer Timing Diagram
388
Table 9-27. IDE Ultradma Data Burst Timing Parameters
389
Figure 9-27. Initiating an Ultradma Data in Burst Timing Diagram
390
Figure 9-28. Sustained Ultradma Data in Burst Timing Diagram
391
Figure 9-29. Host Pausing an Ultradma Data in Burst Timing Diagram
392
Figure 9-30. Device Terminating an Ultradma Data in Burst Timing Diagram
393
Figure 9-31. Host Terminating an Ultradma Data in Burst Timing Diagram
394
Figure 9-32. Initiating an Ultradma Data out Burst Timing Diagram
395
Figure 9-33. Sustained Ultradma Data out Burst Timing Diagram
396
Figure 9-34. Device Pausing an Ultradma Data out Burst Timing Diagram
397
Figure 9-35. Host Terminating an Ultradma Data out Burst Timing Diagram
398
Figure 9-36. Device Terminating an Ultradma Data out Burst Timing Diagram
399
Table 9-28. USB Timing Parameters
400
Figure 9-37. Data Signal Rise and Fall Timing Diagram
402
Figure 9-38. Source Differential Data Jitter Timing Diagram
402
Figure 9-39. EOP Width Timing Diagram
403
Figure 9-40. Receiver Jitter Tolerance Timing Diagram
403
Figure 9-41. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
404
Table 9-29. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters
404
Figure 9-42. Fast IR (mir and FIR) Timing Diagram
405
Table 9-30. Fast IR Port Timing Parameters
405
Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram
406
Table 9-31. Standard Parallel Port Timing Parameters
406
Figure 9-44. Enhanced Parallel Port Timing Diagram
407
Figure 9-45. ECP Forward Mode Timing Diagram
408
Table 9-33. ECP Forward Mode Timing Parameters
408
Figure 9-46. ECP Reverse Mode Timing Diagram
409
Table 9-34. ECP Reverse Mode Timing Parameters
409
Figure 9-47. AC97 Reset Timing Diagram
410
Figure 9-48. AC97 Sync Timing Diagram
410
Table 9-35. AC Reset Timing Parameters
410
Table 9-36. AC97 Sync Timing Parameters
410
Figure 9-49. AC97 Clocks Diagram
411
Table 9-37. AC97 Clocks Parameters
411
Figure 9-50. AC97 Data Timing Diagram
412
Table 9-38. AC97 I/O Timing Parameters
412
Figure 9-51. AC97 Rise and Fall Timing Diagram
413
Table 9-39. AC97 Signal Rise and Fall Timing Parameters
413
Figure 9-52. AC97 Low Power Mode Timing Diagram
414
Table 9-40. AC97 Low Power Mode Timing Parameters
414
Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram
415
Figure 9-54. GPWIO and ONCTL# Timing Diagram
415
Table 9-41. PWRBTN# Timing Parameters
415
Table 9-42. Power Management Event (GPWIO) and ONCTL# Timing Parameters
415
Figure 9-55. Power-Up Sequencing with PWRBTN# Timing Diagram
416
Table 9-43. Power-Up Sequence Using the Power Button Timing Parameters
416
Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram
417
Table 9-44. Power-Up Sequence Not Using the Power Button Timing Parameters
417
Figure 9-57. TCK Measurement Points and Timing Diagram
418
Table 9-45. JTAG Timing Parameters
418
Figure 9-58. JTAG Test Timing Diagram
419
10 0Package Specifications
421
Thermal Characteristics
421
Table 10-1. Q JC (×C/W)
421
Table 10-2. Case-To-Ambient Thermal Resistance Example @ 85×C
421
Figure 10-1. Heatsink Example
422
Physical Dimensions
423
Figure 10-2. BGU481 Package - Top View
423
Figure 10-3. BGU481 Package - Bottom View
424
Appendix A Support Documentation
425
Order Information
425
A.1 Order Information
425
Data Book Revision History
426
Table A-1. Revision History
426
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