AMD SB600 Technical Reference Manual page 133

Field Name
IntrCntrl2Reg1
IntrCntrl2Reg1 register
Field Name
IntrCntrl2Reg2
IntrCntrl2Reg2 register
Field Name
Dma2_Ch4Addr
Dma2_Ch4Addr register
Field Name
Dma2_Ch4Cnt
Dma2_Ch4Cnt register
Field Name
Dma2_Ch5Addr
Dma2_Ch5Addr register
Field Name
Dma2_Ch5Cnt
Dma2_Ch5Cnt register
Field Name
Dma2_Ch6Addr
Dma2_Ch6Addr register
Field Name
Dma2_Ch6Cnt
Dma2_Ch6Cnt register
Field Name
Dma2_Ch7Addr
Dma2_Ch7Addr register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
IntrCntrl2Reg1- RW – 8 bits - [IO_Reg: A0h]
Bits Default
7:0 00h IRQ8 – IRQ15:
Read IRR, ISR
Write ICW1, OCW2, OCW3
IntrCntrl2Reg2- RW – 8 bits - [IO_Reg: A1h]
Bits Default
7:0 00h IRQ8 – IRQ15:
Read IMR
Write ICW2, ICW3, ICW4, OCW1
Dma2_Ch4Addr - RW – 8 bits - [IO_Reg: C0h]
Bits Default
7:0 00h DMA2 Ch4 Base and Current Address
Dma2_Ch4Cnt – RW – 8 bits - [IO_Reg: C2h]
Bits Default
7:0 00h DMA2 Ch4 Base and Current Count
Dma2_Ch5Addr - RW – 8 bits - [IO_Reg: C4h]
Bits Default
7:0 00h DMA2 Ch5 Base and Current Address
Dma2_Ch5Cnt - RW – 8 bits - [IO_Reg: C6h]
Bits Default
7:0 00h DMA2 Ch4 Base and Current Count
Dma2_Ch6Addr - RW – 8 bits - [IO_Reg: C8h]
Bits Default
7:0 00h DMA2 Ch6 Base and Current Address
Dma2_Ch6Cnt - RW – 8 bits - [IO_Reg: CAh]
Bits Default
7:0 00h DMA2 Ch6 Base and Current Count
Dma2_Ch7Addr - RW – 8 bits - [IO_Reg: CCh]
Bits Default
7:0 00h DMA2 Ch5 Base and Current Address
Description
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Description
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Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 133