AMD SB600 Technical Reference Manual page 229

Field Name
Latency Timer
Field Name
Header Type
Field Name
BIST
Lower Base Address Register – RW – 32 bits – [PCI_Reg: 10h]
Field Name
Space Type
Address Range
Prefetchable
Reserved
Lower Base Address
Upper Base Address Register – RW – 32 bits – [PCI_Reg: 14h]
Field Name
Upper Base Address
Field Name
Subsystem Vendor ID
Field Name
Subsystem ID
Field Name
Capabilities Pointer
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Latency Timer – R – 8 bits – [PCI_Reg: 0Dh]
Bits Default
7:0 00h
Header Type – R – 8 bits – [PCI_Reg: 0Eh]
Bits Default
7:0 00h
BIST – R – 8 bits – [PCI_Reg: 0Fh]
Bits Default
15:0 0000h
Bits Default
0 0b
2:1 10b
3 0b
13:4 000h
31:14 00000h
Bits Default
31:0 00000000
h
Subsystem Vendor ID – RW – 16 bits – [PCI_Reg: 2Ch]
Bits Default
15:0 0000h
Subsystem ID – RW – 16 bits – [PCI_Reg: 2Dh]
Bits Default
15:0 0000h
Capabilities Pointer – R – 8 bits – [PCI_Reg: 34h]
Bits Default
7:0 50h
Description
Hardwired to "0".
Description
Hardwired to "0".
Description
Hardwired to "0"
.
Description
Hardwired to "0" to indicate this BAR is located in memory
space only.
Hardwired to 10b to indicate this BAR can be located
anywhere in 64-bit address space.
Hardwired to "0" to indicate this BAR is not prefetchable.
Hardwired to "0".
Lower Base Address for the HD Audio controller's memory
mapped configuration registers. 16K bytes are requested
by hardwiring bits[13:4] to 0.
Description
Upper Base Address for the HD Audio controller's memory
mapped configuration registers.
Description
This register is implemented as write-once register. Any
subsequent writes have no effect.
Description
This register is implemented as write-once register. Any
subsequent writes have no effect.
Description
This register indicates the offset for the capability pointer
Proprietary
HD Audio Controllers Registers
Page 229