Host Pci Bridge Registers (Device 20, Function 4); Table 3-1 Pci-To-Pci Bridge Configuration Registers Summary - AMD SB600 Technical Reference Manual

3.2

Host PCI Bridge Registers (Device 20, Function 4)

Note: Some PCI functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to
0). The diagram below lists these PCI functions and the associated registers.
Function
PCI Bridge (PCIB) has one set of configuration registers in PCI configuration space identified by PCI function
4 on the South Bridge.

Table 3-1 PCI-to-PCI Bridge Configuration Registers Summary

©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
PCI
PCI Stop Clock enable
PCI Bridge Soft Reset Enable
PCI Bus drive strength registers
6Ch
Register Name
Vendor ID
Device ID
PCI Command
PCI Device Status
Revision ID/Class Code
Cache Line Size
Latency Timer
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Latency Timer
IO Base
IO Limit
Secondary Status
Memory Base
Memory Limit
Prefetchable Memory Base
Prefetchable Memory Limit
IO Base Upper 16 Bits
IO Limit Upper 16 Bits
Capability pointer
Reserved
Interrupt Line
Interrupt Pin
Bridge Control
Chip Control
Diagnostic Control
CLK Control
Arbiter Control and Priority Bits
SMLT Performance
PMLT Performance
PCDMA
section 2.3: SMBus Module and ACPI Block (Device 20,
PCI_Reg:
C0h
64h
Host PCI Bridge Registers (Device 20, Function 4)
Proprietary
Offset Address
00h
02h
04h
06h
08h
0Ch
0Dh
0Eh
0Fh
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20h
22h
24h
26h
30h
32h
34h
36h
3Ch
3Dh
3Eh
40h
41h
42h
43h
44h
46h
48h
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