AMD SB600 Technical Reference Manual page 204

Field Name
in DMA Overflow
in DMA Status
out DMA Underflow
out DMA Status
SPDIF Underflow
SPDIF Status
Reserved
Phy Data Incoming
Phy Addr Mismatch
Codec0 Not Ready
Codec1 Not Ready
Codec2 Not Ready
New Frame Starts
Reserved
Audio Gpio Interrupt
Reserved
Interrupt Source Register: Each bit in this register expresses an error flag. "1" indicates the error. Driver can read
status or clear by writing "1". Writing 0 to bit doesn't change its value.
Field Name
in DMA Overflow en.
Audio Status Enable
out DMA Underflow en
Out DMA Underflow
Condition Select
SPDIF Underflow en
SPDIF Status enable
Reserved
Phy in Interrupt en
Phy_addr_mismatch_e
n
Codec0 Not Ready En
Codec1 Not Ready En
Codec2 Not Ready En
New Frame Start En
Set Bus Busy Audio
Audio gpio interrupt en
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Interrupt - RW - 32 bits - [MEM_Reg: 00h]
Bits Default
0 0b Input Channel overflow on the next AC'97 clock - out of FIFO space.
1 0b Set to "1" after finishing an input audio DT data block (if
reg0x04[1]=1 and reg0x08[3]=0).
2 0b Output Channel underflow on the next AC'97 clock – no data in
FIFO
3 0b Set to "1" after finishing an output audio DT data block (if
reg0x04[1]=1 and reg0x08[3]=0).
4 0b SPDIF is out of data
5 0b SPDIF status bit - set to "1" after finishing an SPDIF DT data block
(if reg0x04[5]=1 and reg0x08[5]=0).
7:6 0b
8 0b Got OR'ed Physical register address and data from Codecs
9 0b There is mismatch between in Physical and out Physical address
values
10 0b The Ac97_Phy registers in the master Ac97 codec are not ready for
normal operation
11 0b The Ac97_Phy registers in the 1
for normal operation
12 0b The Ac97_Phy registers in the 2
for normal operation
13 0b This bit is set when new frame starts
14 0b
15 0b When the input audio GPIO interrupt is enabled, input bus slot 12 bit
0 is considered as audio GPIO data. When that is true, if slot 12 is
valid and bit 0 changes, this bit is set to indicate audio GPIO
interrupt.
31:16 0000h
Interrupt Enable- RW - 32 bits - [MEM_Reg: 04h]
Bits Default
0 0b Enable Input Channel overflow interrupt.
1 0b 1- When an input or output audio DT data block is finished, status
will be updated in either DT memory or in reg0x00 (depending on
reg0x08[3]).
0 – Don't update status
2 0b Enable Output channel 0 underflow interrupt.
3 0b 0—Underflow interrupt is asserted only when output DMA FIFO has
zero valid entry.
1—Underflow interrupt is asserted as long as output DMA FIFO
does not have enough valid entries for the coming frame
4 0b Enable SPDIF underflow interrupt.
5 0b 1- When an SPDIF DT data block is finished, status will be updated
in either DT memory or in reg0x00 (depending on reg0x08[5]).
0 – Don't update status
7:6 00b
8 0b Enable "Got Physical register data from Codec" interrupt
9 0b Enable Physical address in/out mismatch interrupt
10 0b Enable Codec0_not_ready interrupt
11 0b Enable Codec1_not_ready interrupt
12 0b Enable Codec2_not_ready interrupt
13 0b Enable new frame start interrupt
14 0b Audio is running (write only). Set/cleared by software.
15 0b Enable audio GPIO interrupt
Description
st
slave Ac97 codec are not ready
nd
slave Ac97 codec are not ready
Description
AC '97 Controller Functional Descriptions
Proprietary Page 204