AMD SB600 Technical Reference Manual page 183

Field Name
PECEnable
Field Name
HostCommand
Field Name
RW
Address
Field Name
Data0
Field Name
Data1
Field Name
DataIndex
Field Name
PEC
Field Name
EnableStatus
Reserved
RemotePowerCycle
RemotePowerUp
RemotePowerDown
RemoteReset
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
HostControl – RW - 8 bits - [ASF_IO: 02h]
Bits Default
7 0b 0: PEC disable
1: PEC enable, enable CRC checking when ASF HC presents
as SM master and SM slave.
HostCommand – RW - 8 bits - [ASF_IO: 03h]
Bits Default
7:0 00h Command to be transmitted by master
SlaveAddress– RW - 8 bits - [ASF_IO: 04h]
Bits Default
0 0b 0: Write
1: Read
7:1 00h Provide the SM address of Slave
Data0– RW - 8 bits - [ASF_IO: 05h]
Bits Default
7:0 00h Contains count or DATA0 field of transaction
Data1– RW - 8 bits - [ASF_IO: 06h]
Bits Default
7:0 00h Contains DATA1 field of transaction
DataIndex– RW - 8 bits - [ASF_IO: 07h]
Bits Default
7:0 00h Index to 32 Data registers.
PEC– RW - 8 bits - [ASF_IO: 08h]
Bits Default
7:0 00h PEC byte to be sent to slave.
ASFStatus– RW - 8 bits - [ASF_IO: 0Ah]
Bits Default
7 0b 1: Reset all the status bit in this register.
0: Enable status bit in this register
6:4 000b
3 0b Power cycle has happened from ASF
2 0b Power up has happened. from ASF
1 0b Power down has happened from ASF
0 0b Reset has happened from ASF
Description
Description
Description
Description
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 183