AMD SB600 Technical Reference Manual page 262

SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h]
Field Name
RestrictedCmdWoAddr
1
RestrictedCmdWoAddr
2
Note: For these registers either the SpiAccessMacRomEn and/or the SpiHostAccessRomEn bit is cleared;
RestrictedCmdWoAddr1 and RestrictedCmdWoAddr2, become read only and cannot be changed.
Field Name
SPIParameters
FifoPtr
TrackMacLockEn
NormSpeed
FastSpeed[1:0]
WaitClkInterval
SetLockCmd
SetUnlockCmd
ByteProgramCmd
SPI_CmdValue0 Register- RW - 32 bits - [Mem_Reg 10h]
Field Name
MacLockCmd0
MacLockCmd1
MacUnlockCmd0
MacUnlockCmd1
Note Either the SpiAccessMacRomEn and/or the SpiHostAccessRomEn bit is cleared. All of these registers
become read only and cannot be changed.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
23:16 00h Same as RestrictedCmd0 except this command does not have
address
31:24 00h Same as RestrictedCmd0 except this command does not have
address
SPI_Cntrl1 Register- RW - 32 bits - [Mem_Reg 0Ch]
Bits Default
7:0 00h This is the TX/RX FIFO port which can take up to 8 bytes. To
send data to SPI ROM, software writes data into this port. To
retrieve data that are received from the SPI ROM, software
reads from this port.
10:8 000b This three bits show the internal pointer location
11 0b When set, the controller will lock the SPI for the MAC when it
has detected a command (from the MAC) matching the value
defined in offset 10h or 11h. Conversely, it will unlock the bus
when it has detected a command (from the MAC) matching the
value defined in offset 12h or 13h
13:12 11b This defines the clock speed for the non-fast read command
00 – Reserved
01 – 33Mhz
10 – 22 Mhz
11 – 16.5Mhz
15:14 01b This defines the clock speed for the fast speed read.
00 – Reserved
01 – 33Mhz
10 – 22 Mhz
11 – 16.5Mhz
21:16 22h Timing parameters used for SPI sharing protocol
22 0b Lock the SPI bus on the next transaction
23 0b Unlock the SPI bus on the next transaction
31:24 00h This is used to compare against the opcode sent out by the
MAC. This is a predefined value to decode for the BYTE
PROGRAM command.
Bits Default
7:0 06h This is used to compare against the opcode sent out by the
MAC. If SPI_Cntrl1[11] is set, the controller will lock the SPI
bus for the MAC. In other words, the MAC has the exclusive
access to the ROM; access by the CPU will be delayed until
this is unlocked. This is to allow the MAC to do certain
sequence of operations without interruption.
15:8 20h Same as MacLockCmd0
23:16 04h This is used to compare against the opcode sent out by the
MAC. If SPI_Cntrl1[11] is set, the controller will unlock the SPI
bus for the MAC. In other words, access by the CPU will be
allowed again.
31:24 04h Same as MacUnlockCmd0
Description
Description
Description
LPC ISA Bridge (Device 20, Function 3)
Proprietary Page 262